MC9S12GRMV1 Datasheet, PDF (200/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-21. Block Register Map (G3) (continued)
Global Address
Register Name
Bit 7
0x0258
PTP
R
0
W
6
5
4
3
2
0
PTP5
PTP4
PTP3
PTP2
0x0259
PTIP
R
0
W
0
PTIP5
PTIP4
PTIP3
PTIP2
0x025A
DDRP
R
0
W
0
DDRP5 DDRP4 DDRP3 DDRP2
0x025B
R
0
0
0
0
0
0
Reserved
W
0x025C
PERP
R
0
W
0
PERP5 PERP4 PERP3 PERP2
0x025D
PPSP
R
0
W
0
PPSP5 PPSP4 PPSP3 PPSP2
0x025E
PIEP
R
0
W
0
PIEP5
PIEP4
PIEP3
PIEP2
0x025F
PIFP
R
0
W
0
PIFP5
PIFP4
PIFP3
PIFP2
0x0260–0x0261 R
Reserved
W
Reserved for ACMP
0x0262–0x0267 R
0
0
0
0
0
0
Reserved
W
0x0268
R
0
0
0
0
PTJ
W
PTJ3
PTJ2
0x0269
R
0
0
0
0
PTIJ3
PTIJ2
PTIJ
W
0x026A
R
0
0
0
0
DDRJ
W
DDRJ3 DDRJ2
0x026B
R
0
0
0
0
0
0
Reserved
W
0x026C
R
0
0
0
0
PERJ
W
PERJ3 PERJ2
= Unimplemented or Reserved
1
PTP1
PTIP1
DDRP1
0
PERP1
PPSP1
PIEP1
PIFP1
0
PTJ1
PTIJ1
DDRJ1
0
PERJ1
Bit 0
PTP0
PTIP0
DDRP0
0
PERP0
PPSP0
PIEP0
PIFP0
0
PTJ0
PTIJ0
DDRJ0
0
PERJ0
MC9S12G Family Reference Manual, Rev.1.23
202
Freescale Semiconductor