MC9S12GRMV1 Datasheet, PDF (211/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4.3.12 ECLK Control Register (ECLKCTL)
Address 0x001C
R
W
Reset:
7
NECLK
1
1 _{Read: Anytime}
Write: Anytime
6
NCLKX2
5
DIV16
4
EDIV4
3
EDIV3
2
EDIV2
1
0
0
0
0
Figure 2-13. ECLK Control Register (ECLKCTL)
Access: User read/write¹
1
0
EDIV1
EDIV0
0
0
Table 2-33. ECLKCTL Register Field Descriptions
Field
Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
6
No ECLKX2—Disable ECLKX2 output
NCLKX2 This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
5
DIV16
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
4-0
EDIV
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
2.4.3.13 IRQ Control Register (IRQCR)
Address 0x001E
R
W
Reset
7
IRQE
0
6
5
4
3
2
0
0
0
0
IRQEN
0
0
0
0
0
Figure 2-14. IRQ Control Register (IRQCR)
Access: User read/write¹
1
0
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
213