MC9S12GRMV1 Datasheet, PDF (387/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
0x003F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Figure 10-15. S12CPMU CPMUARMCOP Register
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
389