MC9S12GRMV1 Datasheet, PDF (182/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
PAD5
PAD4
Table 2-17. Port AD Pins AD7-0 (continued)
• 32 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the
ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to
output.
• 20 TSSOP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when
used with the ACMP function. The ACMP function has no effect on the output state. Refer to
NOTE/2-180 for input buffer control.
• The ADC analog input channel signal AN5 and the related digital trigger input are mapped to this pin.
The ADC function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin. If the SCI0 TXD signal is enabled the I/O state
will depend on the SCI0 configuration.
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin. The TIM forces the I/O state to be an output
for a timer port associated with an enabled output compare.
• 20 TSSOP: The PWM channel 3 signal is mapped to this pin. If the PWM channel is enabled and
routed here the I/O state is forced to output.
• 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The
enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External
Triggers ETRIG3-0”.
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
32 LQFP: ACMPO > GPO
20 TSSOP: TXD0 > IOC3 > PWM3 > GPO
Others: GPO
• 20 TSSOP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin
when used with the ACMP function. The ACMP function has no effect on the output state. Refer to
NOTE/2-180 for input buffer control.
• The ADC analog input channel signal AN4 and the related digital trigger input are mapped to this pin.
The ADC function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
• 20 TSSOP: The SCI0 RXD signal is mapped to this pin. If the SCI0 RXD signal is enabled and routed
here the I/O state will be forced to input.
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin. The TIM forces the I/O state to be an output
for a timer port associated with an enabled output compare.
• 20 TSSOP: The PWM channel 2 signal is mapped to this pin. If the PWM channel is enabled and
routed here the I/O state is forced to output.
• 20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The
enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External
Triggers ETRIG3-0”.
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
20 TSSOP: RXD0 > IOC2 > PWM2 > GPO
Others: GPO
MC9S12G Family Reference Manual, Rev.1.23
184
Freescale Semiconductor