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| MC9S12GRMV1 Datasheet, PDF (575/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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Digital Analog Converter (DAC_8B5V)
17.4.2.1 Control Register (DACCTL)
)
Module Base + 0x0000
R
W
Reset
7
FVR
1
1 Read: Anytime
Write: Anytime
6
5
4
3
2
0
0
0
DRIVE
0
0
0
0
0
= Unimplemented
Figure 17-3. Control Register (DACCTL)
Access: User read/write1
1
0
DACM[2:0]
0
0
Table 17-3. DACCTL Field Description
Field
Description
7
FVR
Full Voltage Range â This bit deï¬nes the voltage range of the DAC.
0 DAC resistor network operates with the reduced voltage range
1 DAC resistor network operates with the full voltage range
Note: For more details see Section 17.5.7, âAnalog output voltage calculationâ.
6
DRIVE
Drive Select â This bit selects the output drive capability of the operational ampliï¬er, see electrical Spec. for
more details.
0 Low output drive for high resistive loads
1 High output drive for low resistive loads
2:0 Mode Select â These bits deï¬ne the mode of the DAC. A write access with an unsupported mode will be ignored.
DACM[2:0] 000 Off
001 Operational Ampliï¬er
100 Unbuffered DAC
101 Unbuffered DAC with Operational Ampliï¬er
111 Buffered DAC
other Reserved
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
577
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