MC9S12GRMV1 Datasheet, PDF (184/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4 PIM Ports - Memory Map and Register Definition
This section provides a detailed description of all PIM registers.
2.4.1 Memory Map
Table 2-18 shows the memory maps of all groups (for definitions see Table 2-2). Addresses 0x0000 to
0x0007 are only implemented in group G1 otherwise reserved.
Table 2-18. Block Memory Map (0x0000-0x027F)
Port
Global
Address
Register
(A)
0x0000 PORTA—Port A Data Register¹
(B)
0x0001 PORTB—Port B Data Register¹
0x0002 DDRA—Port A Data Direction Register¹
0x0003 DDRB—Port B Data Direction Register¹
(C)
0x0004 PORTC—Port C Data Register¹
(D)
0x0005 PORTD—Port D Data Register¹
0x0006 DDRC—Port C Data Direction Register¹
0x0007 DDRD—Port D Data Direction Register¹
E
0x0008 PORTE—Port E Data Register
0x0009
0x000A
:
0x000B
DDRE—Port E Data Direction Register
Non-PIM address range²
(A) 0x000C PUCR—Pull Control Register
(B)
(C)
0x000D Reserved
(D)
E
0x000E
:
0x001B
Non-PIM address range²
0x001C ECLKCTL—ECLK Control Register
0x001D Reserved
0x001E IRQCR—IRQ Control Register
0x001F
0x0020
:
0x023F
Reserved
Non-PIM address range²
Access Reset Value
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
-
-
R/W
0x50
R
0x00
-
-
R/W
0xC0
R
0x00
R/W
0x00
R
0x00
-
-
Section/Page
2.4.3.1/2-205
2.4.3.2/2-205
2.4.3.3/2-206
2.4.3.4/2-207
2.4.3.5/2-207
2.4.3.6/2-208
2.4.3.7/2-209
2.4.3.8/2-209
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2.4.3.11/2-211
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2.4.3.12/2-213
2.4.3.13/2-213
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MC9S12G Family Reference Manual, Rev.1.23
186
Freescale Semiconductor