MC9S12GRMV1 Datasheet, PDF (247/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

2.5 PIM Ports - Functional Description
Port Integration Module (S12GPIMV1)
2.5.1 General
Each pin except BKGD can act as general-purpose I/O. In addition most pins can act as an output or input
of a peripheral module.
2.5.2 Registers
A set of configuration registers is common to all ports with exception of the ADC port (Table 2-91). All
registers can be written at any time, however a specific configuration might not become active.
Example: Selecting a pullup device. This device does not become active while the port is used as a
push-pull output.
Table 2-91. Register availability per port¹
Data
Port (Portx,
PTx)
Input
(PTIx)
Data
Direction
(DDRx)
Pull
Enable
(PERx)
Polarity Wired- Interrupt Interrupt
Select Or Mode Enable Flag
(PPSx) (WOMx) (PIEx) (PIFx)
A
yes
-
yes
-
-
-
-
B
yes
-
yes
-
-
-
-
C
yes
-
yes
yes
-
-
-
-
D
yes
-
yes
-
-
-
-
E
yes
-
yes
-
-
-
-
T
yes
yes
yes
yes
yes
-
-
-
S
yes
yes
yes
yes
yes
yes
-
-
M
yes
yes
yes
yes
yes
yes
-
-
P
yes
yes
yes
yes
yes
-
yes
yes
J
yes
yes
yes
yes
yes
-
yes
yes
AD
yes
yes
yes
yes
yes
-
yes
yes
1 _{Each cell represents one register with individual configuration bits}
2.5.2.1 Data Register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general-purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to 0.
If the data direction register bits are set to 1, the contents of the data register is returned. This is independent
of any other configuration (Figure 2-64).
2.5.2.2 Input Register (PTIx)
This register is read-only and always returns the buffered state of the pin (Figure 2-64).
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
249