I82371MX Datasheet, PDF (99/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
Primary Command Block Offset:
Primary Control Block Offset:
01F0h
03F4h
Secondary Command Block Offset:
Secondary Control Block Offset:
0170h
0374h
Table 7 and Table 8specify the registers as they affect the MPIIX hardware definition.
Table 7. IDE Legacy I/O port definition: Command Block (DCS1# chip select)
I/O Offset
Register Function (Read / Write)
Register
Access
00h
Data
R/W
01h
Error/Features
R/W
02h
Sector Count
R/W
03h
Sector Number
R/W
04h
Cylinder Low
R/W
05h
Cylinder High
R/W
06h
Drive/Head
R/W
07h
Status/Command
R/W
The Data Register is accessed as a 16-bit register for PIO transfers (except for ECC bytes). All other registers
are accessed as 8-bit quantities.
I/O Offset
Table 8. IDE Legacy I/O port definition: Control Block (DCS3# chip select)
Register Function (Read / Write)
Register
Access
00h
Reserved. Not Claimed by MPIIX unless FDC is enabled.
reserved
01h
Reserved. Not Claimed by MPIIX unless FDC is enabled.
reserved
02h
Alt Status / Device control
R/W
03h
Reserved. Not Claimed by MPIIX unless FDC is enabled.
R/W
The MPIIX claims all accesses to the Command Block Range and claims only the Control Block byte 3x4h offset
02h (3x6h) for the selected connector (primary or secondary). Note that the MPIIX only claims cycles to 3x4h
offsets 00h, 01h, and 03h (3x4h, 3x5h, 3x7h) if the corresponding Floppy interface is enabled in the FDC Enable
Register.
4.5.2. ENHANCED TIMING MODES
The MPIIX includes fast timing modes that target local bus implementations. These timing modes are faster than
those possible with ISA based implementations and are controlled with the granularity of the PCI clock. The fast
timing modes may be enabled only for the IDE data ports. All other transactions to the IDE registers are run in
single transaction mode with compatible timings.
Up to 2 IDE devices may be attached to the IDE connector (drive 0 and drive 1). Only one fast timing mode may
be specified, by programming the IDETIM[ISP] and IDETIM[RCT]. This mode may be applied to drive 0, drive 1,
PRELIMINARY
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