I82371MX Datasheet, PDF (130/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
6.0. TESTABILITY
General Test Mode Description
The test modes are decoded from the IRQ[7:5] inputs when TESTIN# is low. Test modes (Table 18) are latched
by a positive assertion of PWROK.
Test Mode
NAND Tree
NAND Tree
Tri-state All Outputs
Table 18. Test Modes
IRQ7
IRQ6
0
x
x
x
1
0
IRQ5
x
0
1
TESTIN#
0
0
0
Tri-State Mode Description
When in the tri-state test mode all outputs and bi-directional pins are tri-stated, including the NAND Tree final
output IORDY.
NAND Tree Test Mode Description
Tri-states all outputs and bi-directional buffers except for IORDY and SMOUT0. Every output buffer except for
IORDY and SMOUT0 is configured as an input in NAND Tree mode and included in the NAND chain. The first
input of the NAND chain is DIOR#, and the NAND chain is routed counter-clockwise around the chip (e.g.
DIOR#, DIOW#, SA7/DCS1#, ...). The last cell in the chain is SMOUT5 and IORDY is the final output. PCICLK,
HCLK, RTCCLK, IORDY, PWROK and TESTIN# are the only input pins not included in the NAND chain. Note
in the table above there are two possible ways to select NAND Tree test mode.
NAND Tree Test Mode Operation
To perform a NAND Tree test, all pins included in the NAND Tree should be driven high, except for the following
pins, which use inverting Schmitt trigger inputs and should be driven low:
Pin #
77
41
78
36
79
80
81
Pin Name
IRQ1
IRQ8#
IRQ9
ZEROWS#
IRQ7
IRQ6
IRQ5
Pin #
82
83
84
85
86
93
94
Pin Name
IRQ4
IRQ3
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
Beginning with DIOR# and working counter-clockwise around the chip, each pin can be toggled and a resulting
toggle observed on IORDY. Once a pin is toggled it must remain in the new state for the remainder of the NAND
Tree test.
130
PRELIMINARY