I82371MX Datasheet, PDF (18/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Signal Name
IRQ8#
IRQ12/M
MIRQ
PIRQ[A,B]#
INTR
NMI
Type
I
5/3V
pu8KΩ
CMOS
I
5V
pu8KΩ
TTL
I
5V
I
5V
pu8KΩ
TTL
O
3.3V
TTL
4mA
od
3.3V
TTL
4mA
PCIRST#
Low
Description
INTERRUPT REQUEST EIGHT SIGNAL: IRQ8# is always
an active low edge triggered interrupt input (i.e. this interrupt
can not be modified by software). This signal is monitored by
the low power ‘Resume Well’ circuitry during suspend.
IRQ8# must remain asserted until after the interrupt is
acknowledged. If the input goes inactive before this time, a
DEFAULT IRQ7 will occur when the CPU acknowledges the
interrupt.
INTERRUPT REQUEST / MOUSE INTERRUPT: In addition
to providing the standard interrupt function (see
IRQ[15,14,11:9,7:3,1] signal description), this pin can be
programmed (via the FDC Enable Register) to provide a
mouse interrupt function.
When the mouse interrupt function is selected, a low-to-high
transition on this signal is latched by the MPIIX and an INTR
is generated to the CPU as IRQ12. An internal IRQ12
interrupt continues to be generated until a PCIRST# or an I/O
read access to address 60h. After a PCIRST#, this signal
provides the standard IRQ12 function.
MOTHERBOARD DEVICE INTERRUPT REQUEST: The
MIRQ signal can be internally connected to interrupts
IRQ[15,14,12:9,7:3]. If MIRQ line and PIRQx# are steered to
the same interrupt, the device connected to the MIRQx
should produce active high, level interrupts.
If the MIRQ line is steered to a given IRQ input to the internal
8259, the corresponding IRQ is masked, unless the Route
Control register is programmed to allow the interrupts to be
shared. This should only be done if the device connected to
the MIRQ line and the device connected to the IRQ line both
produce active high, level interrupts.
PROGRAMMABLE INTERRUPT REQUEST: The PIRQx#
signals can be shared with interrupts IRQ[15,14,12:9,7:3] as
described in the Interrupt Steering section. Each PIRQx# line
has a separate Route Control Register.
CPU INTERRUPT: INTR is driven by the MPIIX to signal the
CPU that an interrupt request is pending and needs to be
serviced. The interrupt controller must be programmed
following PCIRST# to ensure that INTR is at a known state.
NON-MASKABLE INTERRUPT: NMI is used to force a non-
maskable interrupt to the CPU. The MPIIX generates an NMI
when SERR# is asserted, depending on how the NMI Status
and Control Register is programmed.
18
PRELIMINARY