I82371MX Datasheet, PDF (94/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
4.4.4.3. Normal DMA Cycle
An example of an entire PCI DMA cycle is illustrated in Figure 5 for a read of a 16-bit PCI DMA port. The Mobile
PC/PCI DMA device initiates the cycle by asserting REQx#. When the MPIIX receives the PHLDA# signal, the
channel number is passed to the expansion agent serially by the GNT# signal. This is followed by the actual
DMA cycle that starts by performing two 16-bit I/O reads to the PCI DMA port, followed by a 32-bit memory write
to the memory controller. The I/O reads occur with the PCI I/O address of 00h, while the memory write occurs to
the selected memory. Data for the PCI DMA I/O cycles is always transferred on the address/data lines AD[15:0]
for this example (16-bit cycle).
P C IC LK
R E Q [x ]#
GN T[x]#
A D (31:0)
C xB E (3 :0 )#
F R AM E #
IR D Y#
TRDY#
C lock not to scale
REQ Serial Protocol (9 Clocks)
Clock not to scale
GN T Serial Protocol (4 Clocks)
00h rd data
00h rd data
mem
adr
wrt
data
02h 0Ch
16-bit DMA I/O rd #1
02h 0Ch
07h 00h
16-bit DMA I/O rd #2 32-bit m em ory w rite
Figure 5. DMA Write (16-Bit PCI I/O to PCI Memory)
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PRELIMINARY