I82371MX Datasheet, PDF (108/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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4.8.1.3. SMI# Signal Generation
When the SMI_GATE bit is set to a 1 (SYSMGNTC Register), SMI# is asserted when the hardware, software, or
external SMI is asserted. Clearing the SMI_GATE bit causes SMI# to be negated. SMI# is re-asserted when the
SMI_GATE bit is set to a 1, if there is a pending SMI. If simultaneous active set and reset conditions occur the
SMI_GATE reset function is dominant.
The Local Trap source (see Local Standby section) requires that the SMI# signal is asserted at least 3 CPU
CLKs prior to asserting the ready signal (RDY#, BRDY#) that completes the I/O cycle that generated the trap.
Since the CPU’s ready signal is asserted by the MTSC, and the SMI# signal is asserted by MPIIX, this
“synchronous SMI#” timing is guaranteed by the timing of the MPIIX PCI ready generation and the propagation
of the PCI ready through the MTSC.
4.8.1.4. SMI SOURCES
Global Standby Timer
The Global Standby Timer is used to identify when the system is idle. Power management software loads this
timer with a 8-bit count, then starts the timer by writing a 1 to the GSTBY_SMI_EN bit. The counter is
decremented by an 8 second clock to provide a maximum timeout of 34 minutes. When the count expires, an
SMI# request is generated to the SMI logic and the GSTBY_STAT bit is set.
This Global Standby Timer is reloaded with the initial count by the following events:
• Setting the GSTBY_SMI_EN bit (GSMIE Register).
• Globall Standby Timer expires.
• System Events listed in Table 10. These system events can be individually enabled to reload or not reset the
global standby timer. The global enable (SYS_EVENT_EN) can be used to block all events from reseting the
global standby timer.
The Global Standby Timer countdown is stopped when SM_FREEZE=1 in the SYSMGNTC Register.
If the power management software determines that the system can be placed in a “global standby” state, MPIIX
provides a register bit that can be used to indicate, to a future SMI# handler call, that the system is in a global
standby state. (There is no specific global standby state defined by the Intel 430MX PCIset hardware. This is
defined by the system designer.)
Table 10. System Events that Reload Global Timer and SMI# Delay Timers
Enable Bit
System Event
SYS_EVENT_EN
Global enable for all System Events. Setting to 0 prevents all enabled
System Events from reseting the Global Standby Timer.
SYS_EVENT_EN_IRQx
IRQ1, IRQ3–12,14,15.
SYS_EVENT_EN_INTR
Enable INTR to reload timers.
SYS_EVENT_EN_COMRI
Enable the COM Ring Indicate to reload timers.
SYS_EVENT_EN_NMI
Enable the NMI signal to reload timers.
SYS_EVENT_EN_HWSUS
Enable the BATLOW# and SRBTN# signals to reload the timers.
SYS_EVENT_EN_SMI
Enable the SMI# signal to reload the timers.
SYS_EVENT_EN_EXTSMI
Enable the EXTSMI# to reload the timers.
SA# (SYSTEM ACTIVITY)
The SA# (System Activity) signal on MPIIX will always reload the timers.
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