I82371MX Datasheet, PDF (59/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.64. STPCLKHT—STPCLK# High Timer Count
Address Offset:
Default Value:
Attribute:
D7h
00h
Read/Write
The value in this register defines the duration of the STPCLK# negated period when bit 1 in the CLKC Register is
set to 1. The value in this register is loaded into the STPCLK# Timer when STPCLK# is negated. The STPCLK#
timer counts using a 32-us clock with a range of 32 µs to 8 ms.
Bit
Description
7:0
STPCLK_HI_TMR. Bits [7:0] define the duration of the STPCLK# negated period during clock
throttling. 00h is an illegal programmed count.
3.2.65. STPBRKE0—Stop Break Event Enable 0 Register
Address Offset:
Default Value:
Attribute:
D8h
00h
Read/Write
This register enables/disables hardware events as break events to restore system clocks. When a break event
is enabled, the corresponding hardware event activity restores the CPU clock by negating STPCLK# and
reloading the STPCLKHT Register with its intial count.
Bit
Description
7
STPBRK_EN_IRQ7. 1=Enable IRQ7 as a break event.
6
STPBRK_EN_IRQ6. 1=Enable IRQ6 as a break event.
5
STPBRK_EN_IRQ5. 1=Enable IRQ5 as a break event.
4
STPBRK_EN_IRQ4. 1=Enable IRQ4 as a break event.
3
STPBRK_EN_IRQ3. 1=Enable IRQ3 as a break event.
2
Reserved.
1
STPBRK_EN_IRQ1. 1=Enable IRQ1 as a break event.
0
STPBRK_EN_IRQ0. 1=Enable IRQ0 as a break event.
PRELIMINARY
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