I82371MX Datasheet, PDF (42/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.27. PAMB—PROGRAMMABLE ADDRESS MASK B REGISTER
Address Offset:
Default Value:
Attribute:
9Bh
00h
Read/Write
This register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded) for the Programmable
Address Control Registers (PAC[3,2]).
Bit
Description
7:4
Programmable Address Control 3 Mask (PAC3MASK). 1=corresponding address bit is not
used in the address decode. 0=Corresponding address bit is used in the address decode. For
example, mask field=0011 selects a 4-byte range.
3:0
Programmable Address Control 2 Mask (PAC2MASK). 1=corresponding address bit is not
used in the address decode. 0=Corresponding address bit is used in the address decode. For
example, mask field=0011 selects a 4-byte range.
3.2.28. IOCA—I/O CONFIGURATION ADDRESS REGISTER
Address Offset:
Default Value:
Attribute:
9C−9Dh
00h
Read/Write
This register provides an I/O address range to be forwarded to the Extended I/O Bus for accesses to the
configuration space of an integrated I/O device. PCI address bits AD[9:1] are compared to bits [9:1] of this
register. PCI address bits AD[31:10] must be zero for a decode hit.
Bit
Description
15:10
Reserved.
9:1
I/O Configuration Address (IOCA). This field defines a 2-byte I/O address space between 0
Kbyte and 1 Kbyte that will be forwarded to the Extended I/O Bus, if enabled via the IOCAE bit.
0
I/O Configuration Address Enable (IOCAE). 1=Enable bits [9:1] of this register. 0=Disable
(MPIIX does not claim these PCI cycles).
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PRELIMINARY