I82371MX Datasheet, PDF (73/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.2.2. Interval Timer Status Byte Format Register
Register Location:
Default Value:
Attribute:
Counter 0—040h
Counter 1—041h
Counter 2—042h
Bits[6:0]=Undefined, Bit 7=0
Read Only
Each counter's status byte can be read following an Interval Timer Read Back Command. If latch status is
chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the
counter's Counter Access Ports Register returns the status byte.
Bit
Description
7
Counter OUT Pin State: 1=Pin is 1; 0=Pin is 0.
6
Count Register Status: This bit indicates when the last count written to the Count Register
(CR) has been loaded into the counting element (CE). 0=Count has been transferred from CR to
CE and is available for reading. 1=Count has not been transferred from CR to CE and is not yet
available for reading.
5:4
Read/Write Selection Status: Bits[5:4] reflect the read/write selection made through bits[5:4] of
the Control Register.
Bit[5:4]
00
01
10
11
Function
Counter Latch Command
R/W Least Significant Byte (LSB)
R/W Most Significant Byte (MSB)
R/W LSB then MSB
3:1
Mode Selection Status: Bits[3:1] return the counter mode programming.
Bit[3:1] Mode Selected
Bit[3:1] Mode Selected
000
0
001
1
X10
2
X11
3
100
4
101
5
0
Countdown Type Status: 0=Binary countdown; 1=Binary coded decimal (BCD) countdown.
3.3.2.3. Counter Access Ports Register
Register Location:
Default Value:
Attribute:
Counter 0, System Timer—040h
Counter 1, Refresh Request—041h
Counter 2, Speaker Tone—042h
All bits undefined
Read/Write
Each of these I/O ports is used for writing count values to the Count Registers; reading the current count value
from the counter by either an I/O read, after a counter-latch command, or after a Read Back Command; and
reading the status byte following a Read Back Command.
PRELIMINARY
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