I82371MX Datasheet, PDF (63/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Register
Counter
2F
30
31
32
33
34
35
36
37
38
39
AT I/O
address
A1
A0
70
03FAh
02FAh
03EAh
02EAh
40h
40h
20h
A0h
Description
PIC2 ICW4.
PIC2 OCW2.
OTHER.
NMI mask / RTC address.
COM1 FIFO Enable Register bits 0, 3, 6, 7 (other bits undefined).
COM2 FIFO Enable Register bits 0, 3, 6, 7 (other bits undefined).
COM3 FIFO Enable Register bits 0, 3, 6, 7 (other bits undefined).
COM4 FIFO Enable Register bits 0, 3, 6, 7 (other bits undefined).
TIMER 0 Count Register (low byte).
TIMER 0 Count Register (high byte).
Master PIC OCW3 Register (bits 0,2,5).
Slave PIC OCW3 Register (bits 0,2,5).
Total 58 Registers.
3.2.69. BSTCLKEE[6:0]—Burst Clock Event Enable Registers
Address Offset:
Default Value:
Attribute:
E4h (BSTCLKEE0) to EAh (BSTCLKEE6)
00h
Read/Write
These registers enable various activities as Burst Clock Events. Setting a bit to 1 enables the corresponding
activity as a Burst Clock Event. When activity is detected, STPCLK# is negated, if necessary, and the Burst
Clock Timer is reloaded. The Burst Clock Event Enable bit (bit 0, BSTCLKEE2 register) globally enables these
events.
Bit
BSTCLK
BSTCLK
ENVT
ENVT
EN_6
EN_5
7
Audio-E
COM4
6
Audio-D
COM3
5
Audio-C
COM2
4
Audio-B
COM1
3
Audio-A
FDC-S
2
Parallel-3 FDC-P
1
Parallel-2 IDE-S
0
Parallel-1 IDE-P
BSTCLK
ENVT
EN_4
PMAC1
PMAC0
PAC5
PAC4
PAC3
PAC2
PAC1
PCSC
BSTCLK
ENVT
EN_3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BSTCLK
ENVT
EN_2
Reserved
EXTSMI#
SMI#
Reserved
Reserved
Reserved
EXTEVNT
#
PHLDA#
COMRI#
Burst
Clock
BSTCLK
ENVT
EN_1
IRQ15
IRQ14
Reserved
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8#
BSTCLK
ENVT
EN_0
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
Reserve
d
IRQ1
IRQ0
PRELIMINARY
63