I82371MX Datasheet, PDF (81/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.5.2. NMI Enable and Real-Time Clock Address Register
Register Location:
Default Value:
Attribute:
070h
Bit[6:0]=undefined, Bit 7=1
Write Only
This port is shared with the real-time clock. Do not modify the contents of this register without considering the
effects on the state of the other bits. Reads and writes to this register address flow through to the Extended I/O
Bus.
Bit
Description
7
NMI Enable. 1=Disable all NMI sources. 0=Enable the NMI interrupt.
6:0
Real Time Clock Address. Used by the Real Time Clock on the Base I/O component to address
memory locations. Not used for NMI enabling/disabling.
3.3.5.3. Coprocessor Error Register
Register Location:
Default Value:
Attribute:
F0h
Undefined
Write only
Writing to this register causes the MPIIX to assert IGNNE#. The MPIIX also negates IRQ13 (internal to the
MPIIX). Note, that IGNNE# is not asserted unless FERR# is active. Reads/writes flow through to the Extended
I/O Bus.
Bit
Description
7:0
No special pattern required: A write to address F0h executes the command.
3.3.5.4. RC—Reset Control Register
I/O Address:
Default Value:
Attribute:
CF9h
00h
Read/Write
Bits 1 and 2 in this register are used by the MPIIX to generate a hard reset or a soft reset. To perform a proper
reset, bit 2 should be cleared when writing the type of reset (bit 1) to be performed. Then bit 2 should be set to
initiate the reset. To perform a soft (hard) reset, first a 00h (02h) is written to CF9h. A second write of 04h (06h)
is written to initiate the soft (hard) reset.
Bit
Description
7:4
Reserved.
3
Reserved.
2
Reset CPU (RCPU): This bit is used to initiate (transitions from 0 to 1) a hard reset (bit 1 in this
register is set to 1) or a soft reset to the CPU. During a hard reset, the MPIIX asserts CPURST,
PCIRST#, and RSTDRV. The MPIIX initiates a hard reset when this register is programmed for a
hard reset or PWROK is asserted. This bit cannot be read as a 1.
PRELIMINARY
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