I82371MX Datasheet, PDF (98/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
4.5. IDE Interface
The MPIIX integrates a high performance interface from PCI to IDE that is capable of accelerated PIO data
transfers. The MPIIX provides an interface for one IDE connector that can be configured as either the primary or
secondary IDE connector (Figure 9).
MPIIX
SA[15:8]
DOE#,
SA7,
SD [7:0] SD IR SA[2:0] _SA6
DIOR#,
IO RD Y ^{DIOW # IR Q}
SA[15:8]
ALS245
DD [15:0]
ALS244
D A[2:0]
DCS1#
DCS3#
IDE Connector
Figure 9. MPIIX IDE Interface
052509
The IDE data transfer command strobes, DMA request and grant signals, and IORDY signal interface directly to
the MPIIX. The IDE data lines (DD[15:0]) are buffered versions of the SD[7:0] system data lines and the
multiplexed SA[15:8] system address lines. The IDE data buffer uses the same direction control signal (SDIR) as
the PCS# interface and an output enable (DOE#). (DOE# shares a pin with SMOUT5 and must be configured
as the DOE# pin.) The IDE address and chip select output signals are multiplexed on the SA[7,6,2:0] lines.
4.5.1. ATA REGISTER BLOCK DECODE
The IDE ATA I/O port is decoded by the MPIIX when the decode is enabled for either the primary connector or
the secondary connector in the IDE Timing Register (IDETIM). The actual ATA registers are implemented in the
drive itself. An access to the IDE registers results in the assertion of the appropriate chip select for the register.
The transaction is then run using compatible timing and using the IDE command strobes (DIOR#, DIOW#).
There are two I/O ranges; the Command block (8-byte range) that corresponds to the DCS1# chip select and the
Control block (4-byte range) that corresponds to the DCS3# chip select. The upper 15 bits of the I/O address
(SA[17:3]) are decoded as all zeros.
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PRELIMINARY