I82371MX Datasheet, PDF (31/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.9. ECRT— EXTENDED I/O CONTROLLER RECOVERY TIMER REGISTER
Address Offset:
Default Value:
Attribute:
4Ch
48h
Read/Write
The I/O recovery mechanism in the MPIIX is used to add additional recovery delay between PCI Master
originated 8-bit cycles to the Extended I/O Bus. The MPIIX automatically forces a minimum delay of 3.5
SYSCLKs between back-to-back 8-bit I/O cycles to the Extended I/O bus. This delay is measured from
the rising edge of the I/O command (IOR# or IOW#) to the falling edge of the next I/O command . If a
delay of greater than 3.5 SYSCLKs is required, the Extended I/O Recovery Time Register can be
programmed to increase the delay in increments of SYSCLKs. No additional delay is inserted for back-to-
back I/O "sub cycles" generated as a result of byte assembly or disassembly. This register defaults to 8-
bit recovery enabled with one SYSCLK clock added to the standard I/O recovery.
Bit
Description
7
Reserved.
6
8-Bit I/O Recovery Enable. 1=Enable the recovery time programmed in bits [5:3]. 0=Disable
recovery times in bits [5:3] and the recovery timing of 3.5 SYSCLKs is inserted.
5:3
8-Bit I/O Recovery times. When bit 6=1, this 3-bit field defines the recovery time for 8-bit I/O.
Bit [5:3]
001
010
011
100
SYSCLK
1 (default)
2
3
4
Bit [5:3]
101
5
110
111
000
SYSCLK
6
7
8
2
16-Bit I/O Recovery Enable. Reserved. Read as 0.
1:0
16-Bit I/O Recovery Times. Reserved. Read as 0.
3.2.10. BIOSE — BIOS ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
4Eh
08h
Read/Write
This register enables/disables BIOS accesses to the different segments. This register also controls the
generation of the BIOSCS# signal.
Bit
Description
7
Extended BIOS Enable. When bit 7=1 (enabled), PCI master accesses to locations
FFFC0000h–FFFDFFFFh are forwarded to the Extended I/O Bus and BIOSCS# is generated.
When bit 7=0, the MPIIX does not claim the cycle or generate BIOSCS#.
6
Lower BIOS Enable 1. When bit 6=1 (enabled), PCI master accesses to locations 0E4000h–
000EFFFFh (and alias at 4G) are forwarded to the Extended I/O Bus and BIOSCS# is generated.
When bit 6=0, the MPIIX does not claim the cycle or generate BIOSCS#.
5
Lower BIOS Decode Enable 0. When bit 5=1 (enabled), PCI master accesses to locations
0E0000h–000E3FFFh (and alias at 4G) are forwarded to the Extended I/O Bus. This region is
also used for Kanji BIOS. When bit 5=0, the MPIIX does not claim the cycle.
PRELIMINARY
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