I82371MX Datasheet, PDF (60/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.66. STPBRKE1—Stop Break Event Enable 1 Register
Address Offset:
Default Value:
Attribute:
D9h
00h
Read/Write
This register enables/disables hardware events as break events to restore system clocks. When a break event
is enabled, the corresponding hardware event activity restores the CPU clock by negating STPCLK# and
reloading the STPCLKHT Register with its intial count.
Bit
Description
7
STPBRK_EN_IRQ15. 1=Enable IRQ15 as a break event.
6
STPBRK_EN_IRQ14. 1=Enable IRQ14 as a break event.
5
Reserved.
4
STPBRK_EN_IRQ12. 1=Enable IRQ12 as a break event.
3
STPBRK_EN_IRQ11. 1=Enable IRQ11 as a break event.
2
STPBRK_EN_IRQ10. 1=Enable IRQ10 as a break event.
1
STPBRK_EN_IRQ9. 1=Enable IRQ9 as a break event.
0
STPBRK_EN_IRQ8. 1=Enable IRQ8# as a break event.
3.2.67. STPBRKE2—Stop Break Event Enable 2 Register
Address Offset:
Default Value:
Attribute:
DAh
00h
Read/Write
This register enables/disables hardware events as break events to restore system clocks. When a break event
is enabled, the corresponding hardware event activity restores the CPU clock by negating STPCLK# and
reloading the STPCLKHT Register with its intial count. This register also disables all break events.
Bit
Description
7
STPBRK_EN_HWSUS. 1=Enable SRBTN# and BATLOW# as break events. For these signals
to be recognized as break events, the corresponding SMIs musts be enabled in the MISCSMIE
Register.
6
STPBRK_EN_EXTSMI. 1=Enable EXTSMI# as a break event. For this signal to be recognized
as break event, SMIs must be enable for EXTSMI# in the SYSSMIE Register.
5
STPBRK_EN_SMI. 1=Enable SMI# as a break event.
4
STPBRK_EN_NMI. 1=Enable NMI as a break event.
3
STPBRK_EN_INTR. 1=Enable INTR as a break event.
2
Reserved.
1
STPBRK_EN_COMRI. 1=Enable COMRI# as a break event.
0
STPBRK_EN. 0=Disable all break events. 1=Break events are enabled by their respective
enables.
60
PRELIMINARY