I82371MX Datasheet, PDF (45/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
4
3
2
1
0
Description
LTRP_SMI_EN_AUD. 1=Enable. 0=Disable.
LTRP_SMI_EN_COM. 1=Enable. 0=Disable. (The address range is defined by the LTMDEV3
Register.)
LTRP_SMI_EN_DEV3. 1=Enable. 0=Disable. (The address range is defined by the LTADEV3
and LTMDEV3 Registers.)
LTRP_SMI_EN_DEV2. 1=Enable. 0=Disable. (The address range is defined by the PAC1 and
PAMA Registers.)
LTRP_SMI_EN_DEV1. 1=Enable. 0=Disable. (The address range is defined by the PCSC and
PAMA Registers.)
3.2.34. LTSMIS—Local Trap SMI Status Register
Address Offset:
Default Value:
Attribute:
AEh
00h
Read/Write
This register indicates that an access to the corresponding enabled local trap caused an SMI# request. The
traps are enabled via the LTSMIE Register. The MPIIX sets the request status bits to a 1. Software clears a bit
by writing a 0 to it. If MPIIX is setting the bit to a 1 at the same time that software is setting it to 0, the bit is set to
1. The address range for each bit is defined in Section 4.8.3.2, Access Ranges.
Bit
Description
7:6
Reserved.
5
LTRP_STAT_IDE.
4
LTRP_STAT_AUD.
3
LTRP_STAT_COM. The address range is defined by the LTMDEV3 Register.
2
LTRP_STAT_DEV3. The address range is defined by LTADEV3 and LTMDEV3 Registers.
1
LTRP_STAT_DEV2. The address range is defined by PAC1 and PAMA Registers.
0
LTRP_STAT_DEV1. The address range is by the PCSC and PAMA Registers.
3.2.35. LSBSMIE—Local Standby SMI Enable Register
Address Offset:
Default Value:
Attribute:
B0h
00h
Read/Write
When a bit in this register is set to 1, the corresponding Local Standby timer is reloaded with the initial count and
begins to count down. An access to the corresponding local trap address reloads the timer. When the timer
expires, an SMI# is generated, if enabled in the GSMIE Register. When a bit is set to 0, the corresponding timer
does not count down. The address range for each bit is defined in Section 4.8.3.2, Access Ranges.
Bit
Description
PRELIMINARY
45