I82371MX Datasheet, PDF (86/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Address
000E0000–000E3FFFh
FFFE0000–FFFE3FFFh
000E0000–000FFFFFh
FFFE0000–FFFFFFFFh
FFFC0000–FFFDFFFFh
Type
R/W
R/W
R/W
R/W
Name
Kanji BIOS (at top of 1MB)
Kanji BIOS (at top of 4 GB)
BIOS Memory (128 KB at top of 1MB)
BIOS Memory (aliased 128 KB region at top
of 4 GB)
BIOS Memory (additional 128 KB region at
top of 4 GB)
Encoded Chip
Select
BIOSCS#
(optional)
BIOSCS#
(optional)
BIOSCS#
BIOSCS#
BIOSCS#
4.2. PCI Interface
The MPIIX incorporates a fully PCI Bus compatible master and slave interface. As a PCI master, the MPIIX runs
cycles on behalf of DMA. As a PCI slave, the PIIX accepts cycles intitiated by PCI masters targeted for the
MPIIX’s internal registers or the Extended I/O Bus. The MPIIX directly supports the PCI interface running at
either 25 Mhz, 30 Mhz, or 33 MHz.
Bus commands indicate to the slave the type of transaction the master is requesting. Bus Commands are
encoded on the C/BE[3:0]# lines during the address phase of a PCI cycle.
4.2.1. TRANSACTION TERMINATION
The MPIIX supports both Master-initiated Termination as well as Target-initiated Termination.
MPIIX As MasterMaster-Initiated Termination
The MPIIX supports three forms of Master-initiated Termination:
1. Normal termination of a completed transaction.
2. Normal termination of an incomplete transaction due to timeout.
3. Abnormal termination due to no slave responding to the transaction (master abort).
MPIIX As a MasterResponse to Target-Initiated Termination
MPIIX's response as a master-to-target-termination, including target abort, retry, and disconnect.
MPIIX As a TargetTarget-Initiated Termination
The MPIIX supports three forms of Target-initiated Termination (target abort, retry, and disconnect).
4.2.2. PARITY SUPPORT
As a master, the MPIIX generates address parity for read and write cycles, and data parity for write cycles. As a
slave, the MPIIX generates data parity for read cycles. The MPIIX does not check parity and does not generate
SERR#.
86
PRELIMINARY