I82371MX Datasheet, PDF (65/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.1.1. DCOM—DMA Command Register
Register Location:
Default Value:
Attribute:
Channels 0−3—08h
Channels 4−7—0D0h
00h
Write Only
This 8-bit register controls the configuration of the DMA. Note that disabling channels 4-7 also disables channels
0-3, since channels 0-3 are cascaded onto channel 4.
Bit
Description
7
DACK# ACTIVE Level (DACK[3:0,7:5]#). This bit is hardwired to 0. DACK[3:0,7:5]# are always
active low.
6
DREQ Sense Assert Level (DREQ[3:0,7:5]). This bit is hardwired to 0. DREQ[3:0,7:5] are
always active high.
5
Reserved. Must be 0.
4
DMA Group Arbitration Priority. 1=Rotating priority. 0=Fixed priority.
3
Reserved. Must be 0.
2
DMA Channel Group Enable. 1=Disable. 0=Enable.
1:0
Reserved. Must be 0.
3.3.1.2. DCM—DMA Channel Mode Register
Register Location:
Default Value:
Attribute:
Channels 0−3—0Bh
Channels 4−7—0D6h
Bits[7:2]=0, Bits[1:0]=undefined
Write Only
Each channel has a DMA Channel Mode Register. The Channel Mode Registers provide control over DMA
transfer type, transfer mode, address increment/decrement, and autoinitialization. This register is set to its
default state upon PCIRST or Master Clear.
Bit
Description
7:6 DMA Transfer Mode: Each DMA channel can be programmed in one of four different modes.
Note that channels programmed for block or cascade mode or channels that are used for PCI
DMA can not be programmed for type F timing mode.
Bits[7:6]
00
01
10
11
Transfer Mode
Demand mode
Single mode
Block mode
Cascade mode
5
Address Increment/Decrement Select: 0=Increment; 1=Decrement.
4
Autoinitialize Enable: 1=Enable; 0=Disable.
PRELIMINARY
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