I82371MX Datasheet, PDF (64/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Event
Enable
3.2.70. CLKTHLBRKEE[6:0]—Clock Throttle Break Event Enable Registers
Address Offset:
Default Value:
Attribute:
ECh (CLKTHLBRKEE0) to F2h (CLKTHLBRKEE6)
00h
Read/Write
These registers enable various activities as Clock Throttle Break Events. Setting a bit to 1 enables the
corresponding activity as a Clock Throttle Break Event. When activity is detected, STPCLK# is negated, if
necessary, and the Clock Throttle Standby Timer reloaded. The CLKTHLBRKE Enable bit (bit 0,
CLKTHLBRKEE2 register) globally enables these events.
Bits
7
CLKTHL
BRKEVNT
EN_6
Audio-E
6
Audio-D
5
Audio-C
4
Audio-B
3
Audio -A
2
Parallel-3
1
Parallel-2
0
Parallel-1
CLKTHL
BRKEVNT
EN_5
Serial-4
Serial-3
Serial-2
Serial-1
FDC-S
FDC-P
IDE-S
IDE-P
CLKTHL
BRKEVNT
EN_4
PMAC1
PMAC0
PAC5
PAC4
PAC3
PAC2
PAC1
PCSC
CLKTHL
BRKEVNT
EN_3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EXTEVNT#
PHLDA#
CLKTHL
BRKEVNT
EN_2
BATLOW#
/SRBTN#
EXTSMI#
SMI#
NMI
INTR
Reserved
COMRI#
CLKTHL
BRKEVNT
Enable
CLKTHL
BRKEVNT
EN_1
IRQ15
IRQ14
Reserved
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8#
CLKTHL
BRKEVNT
EN_0
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
Reserved
IRQ1
IRQ0
3.3. ISA Compatible Registers
The ISA Compatible registers contain the DMA, timer/counter, and interrupt registers. This group also contains
the NMI, and reset registers.
3.3.1. DMA REGISTERS
The MPIIX contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers (DMA1 and
DMA2). The DMA registers control the operation of the DMA controllers and are all accessible via the PCI Bus
interface. This section describes the DMA registers. Unless otherwise stated, a PCIRST sets each register to
its default value.
64
PRELIMINARY