I82371MX Datasheet, PDF (118/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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Off-to-On Transition: Power management software enables the Local Trap hardware by setting the Local Trap
SMI enable. When the system requires an I/O access to that device range, the access is trapped, an SMI# is
generated, and the corresponding Local Trap SMI request indication bit are set. (Both the global Local Trap SMI
Request status and the specific Local Trap SMI Request status bits are set.) The software then places the
peripheral device in an on state, clears the Local Trap SMI status bits, then enables the Local Standby Idle
Timer hardware.
4.8.3.2. Access Ranges
The IDE and Audio ranges are selected when the devices are configured, so no further action is required to
setup these ranges prior to enabling the access monitoring or trapping. The COM port and programmable trap
ranges must be setup prior to enabling the access monitoring or trapping.
• IDEI/O address range trap, for either the Primary or Secondary IDE ranges, whichever is enabled.
 1F0h to 1F7h, 3F4h to 3F7h I/O reads and writes are trapped if the primary interface is enabled.
 170h to 177h, 374h to 377h I/O reads and writes are trapped if the secondary interface is enabled.
• Audio and FM SynthesisI/O address traps.
 0201h, 02x0h–02xFh, 388h–38Bh I/O reads and writes where x= 2, 3, 4, or 5.
 2xAh, 2xEh – I/O reads where x= 2, 3, 4, or 5.
 MDAK1 or MDAK2 can be enabled to cause the Audio Local Standby timer to be reloaded.
• COM portsOne or all of the following I/O address options are selected by programming the LTMDEV3
Register. When an access occurs to an enabled range, the Local Standby COM Timer is re-loaded.
 3F8–3FFh.
 2F8–2FFh.
 2E8–2EFh.
 3E8–3EFh.
• Three Programmable I/O Address traps for CPU driven cycles on the PCI Bus.
 16-bit I/O port base register, for PCI I/O address bits [15:0]. (TRP_ADR_xxx).
• DEV1 uses Extended I/O Programmable Chip Select (PCS#) Range.
• DEV2 uses Extended I/O decode Programmable Address Range #1.
• DEV3 uses a independent Local Trap Address Range.
 4-bit I/O port mask register, for PCI I/O address bits [3:0]. (TRP_MSK_xxx).
 The PCI trap logic compares the 16 least significant bits, while checking that PCI I/O address bits [31:16]
are all 0. This provides address trapping of the PCI low 64 Kbytes, while not aliasing in address ranges
above 64 Kbytes.
4.8.3.3. Idle Timers
MPIIX provides 6 idle timers (three timers for the programmable device access ranges, one timer per IDE, COM
and Audio/FM). When an idle timer is enabled, it will count down until its corresponding access monitor detects
device activity. At that time, the timer is reloaded with the initial count. If the timer expires, an SMI# is generated.
Enable: The Local Standby Idle Timers are globally enabled by setting the LSTBY_SMI_EN bit in the GSMIE
Register. When this bit is set to 1, the enabling of the individual timer is controlled by the LSTBY_SMI_EN_xxx
for that specific device.
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PRELIMINARY