I82371MX Datasheet, PDF (76/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.3.3.5. ICW4—Initialization Command Word 4 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—021h
INT CNTRL-2—0A1h
01h
Write Only
Both MPIIX interrupt controllers must have ICW4 programmed as part of their initialization sequence.
Bit
Description
7:5
Reserved: Must be programmed to all 0s.
4
Special Fully Nested Mode (SFNM): Bit 4, SFNM, should normally be disabled by writing a 0
to this bit. If SFNM=1, the special fully nested mode is programmed.
3
Buffered mode (BUF): Must be programmed to 0 selecting non-buffered mode.
2
Master/Slave in Buffered Mode: Should always be programmed to 0. Bit not used.
1
AEOI (Automatic End of Interrupt): This bit should normally be programmed to 0. This is the
normal end of interrupt. If this bit is 1, the automatic end of interrupt mode is programmed.
0
Microprocessor Mode: Must be programmed to 1 indicating an Intel Architecture-based
system.
3.3.3.6. OCW1—Operational Control Word 1 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—021h
INT CNTRL-2—0A1h
00h
Read/Write
OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR). Each interrupt request line may be
selectively masked or unmasked any time after initialization. The IMR stores the interrupt line mask bits. The
IMR operates on the IRR. Masking of a higher priority input does not affect the interrupt request lines of lower
priority. Unlike status reads of the ISR and IRR, for reading the IMR, no OCW3 is needed. The output data bus
contains the IMR when an I/O read is active and the I/O address is 021h or 0A1h (OCW1). All writes to OCW1
must occur following the ICW1-ICW4 initialization sequence, since the same I/O ports are used for OCW1,
ICW2, ICW3 and ICW4.
Bit
Description
7:0
Interrupt Request Mask (Mask [7:0]). When a 1 is written to any bit in this register, the
corresponding IRQx line is masked. For example, if bit 4 is set to a 1, then IRQ4 is masked.
Interrupt requests on IRQ4 do not set channel 4's interrupt request register (IRR) bit as long is the
channel is masked. When a 0 is written to any bit in this register, the corresponding IRQx is
unmasked. Note that masking IRQ2 on CNTRL-1 also masks the interrupt requests from CNTRL-
2, which is physically cascaded to IRQ2.
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PRELIMINARY