I82371MX Datasheet, PDF (29/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
10:9
8
7
6:0
Description
DEVSEL# Timing Status (DEVT): DEVT=01. The MPIIX always generates DEVSEL# with
medium timing for Extended I/O functions. This DEVSEL# timing does not include
configuration cycles.
PERR# Response (Not Implemented). Read as 0.
Fast Back to BackRO. This bit is read as 1, indicating to the PCI Master that MPIIX, as a
target, is capable of accepting fast back-to-back transactions.
Reserved. Read as 0s.
3.2.5. RID—REVISION IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
08h
Refer to stepping information
Read Only
This 8-bit register contains device stepping information. Writes to this register have no effect.
Bit
Description
7:0
Revision ID Byte: The register is hardwired to the default value.
3.2.6. CLASSC—CLASS CODE REGISTER
Address Offset:
Default Value:
Attribute:
09−0Bh
068000h
Read Only
This register contains the device programming interface information related to the Sub-Class Code and Base
Class Code definition for the MPIIX. This register also identifies the Base Class Code and the function sub-class
in relation to the Base Class Code.
Bit
Description
23:16
Base Class Code (BASEC). 06h=PCI Bridge device.
15:8
Sub-Class Code (SCC). 01h=Other bridge device (ISA-like Extended I/O Bus).
7:0
Programming Interface (PI). 00h=No programming interface defined.
PRELIMINARY
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