I82371MX Datasheet, PDF (95/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
4.4.4.4. Normal DMA Cycle with Terminal Count
The terminal count protocol for ending demand mode transfers (larger than a single transfer) is shown in
Figure 6 for a write transfer from a 16-bit PCI I/O to PCI memory. When a DMA device initiates a multi-byte
transfer, the DMA Controller passes a Terminal Count (TC) indication that the device is making its last transfer.
The TC indication, that all requesting devices must recognize, is an I/O cycle (read or write, depending on
whether the I/O portion was a load or store) by the DMA controller to address 04h. When the DMA I/O device or
expansion agent detects a TC, it negates its REQ#. The MPIIX recognizes the removal of the request for service
and removes its GNTx#, which cascades back through the PCI DMA agent to the initiating device.
PC IC LK
R E Q[x ]#
GN T[x]#
AD (31:0)
C xBE[3:0]#
FRAM E#
IR DY#
TRDY#
Clock no t to sca le
R E Q Se rial P ro to col (9 C loc ks)
Clock no t to sca le
GN T S erial P ro tocol _{(4 C loc ks)}
00 h rd data
04 h ^{rd data}
mem
adr
wrt data
02h 0Ch
16-bit DMA I/O rd #1
02h 0Ch
16-bit DMA I/O rd #2
07h 00h
3 2-bit m em o ry w rite
Figure 6. Terminal Count of DMA Write (16-Bit PCI I/O to PCI Memory)
052506
PRELIMINARY
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