I82371MX Datasheet, PDF (28/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.3. COM—COMMAND REGISTER
Address Offset:
Default Value:
Attribute:
05–04h
0007h
Read/Write
This 16-bit register provides basic control over the MPIIX's ability to respond to PCI cycles.
Bit
Description
15:10
Reserved. Read as 0.
9
Fast Back-to-Back Enable (FBE). Reserved, read as 0.
8
SERR# Enable. Reserved, read as 0.
7:5
Reserved. Read as 0.
4
Postable Memory Write Enable (PMWE). This bit will always be read as a 0.
3
Special Cycle Enable (SCE). 1=Enable (MPIIX recognizes PCI special cyclesshutdown and
stop grant); 0=Disable (MPIIX ignores all PCI special cycles).
2
Bus Master Enable (BME). MPIIX does not support disabling its bus master capability. This bit
always reads as 1.
1
Memory Space Enable (MSE). The MPIIX does not support disabling access to main memory.
This bit is read as 1.
0
I/O Space Enable (IOSE). The MPIIX does not support disabling its response to PCI I/O
cycles. This bit is read as 1.
3.2.4. DS—DEVICE STATUS REGISTER
Address Offset:
Default Value:
Attribute:
06−07h
0280h
Read/Write Clear
DSR is a 16-bit status register that reports the occurrence of a PCI master-abort by the MPIIX or a PCI target-
abort when the MPIIX is a master. The register also indicates the MPIIX DEVSEL# signal timing.
Bit
Description
15
Parity Error (Not Implemented). Read as 0.
14
SERR# Status (Not Implemented). Read as 0.
13
Master-Abort Status (MA): When the MPIIX, as a master, generates a master-abort, MA is
set to a 1. Software sets MA to 0 by writing a 1 to this bit location.
12
Received Target-Abort Status (RTA): When the MPIIX is a master on the PCI Bus and
receives a target-abort, this bit is set to a 1. Software resets RTA to 0 by writing a 1 to this bit
location.
11
Signaled Target-Abort Status (STA): This bit is set when the MPIIX Extended I/O bus bridge
function is targeted with a transaction that the MPIIX terminates with a target abort. Software
resets STA to 0 by writing a 1 to this bit location.
28
PRELIMINARY