I82371MX Datasheet, PDF (13/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
2.2. IDE Interface Signals
Signal Name
Type
PCIRST#
DD[15:8]/
SA[15:8]/
SD[15:8]
I/O
O
5V
TTL
8mA
Undefined
DD[7:0]/
SD[7:0]
I/O
I/O
5V
TTL
8mA
Tri-state
DIOR#
O
5V
TTL
8mA
High
DIOW#
O
5V
TTL
8mA
High
IORDY
I
5V
pu8KΩ
DA[2:0]/
SA[2:0]
O
5V
TTL
8mA
Undefined
DCS1#,
DCS3# /
SA7,SA6
O
5V
TTL
8mA
Undefined
DOE# /
SMOUT5
O
5V
TTL
4mA
High
Description
DISK DATA: These signals directly drive the
corresponding signals on the IDE connector. In addition,
these signals are externally buffered to produce the
SA[15:8] signals (see separate descriptions).
DISK DATA: These signals directly drive the
corresponding signals on the IDE connector. In addition,
these signals are externally buffered to produce the
SD[7:0] signals (see separate descriptions).
DISK I/O READ: This signal directly drives the
corresponding signal on the IDE connector.
DISK I/O WRITE: This signal directly drives the
corresponding signal on the IDE connector.
IO CHANNEL READY: This input signal is directly driven
by the corresponding signal on the IDE connector.
DISK ADDRESS: These address signals directly drive
the DA[2:0] signals on the IDE connector and are used to
indicate which byte in the ATA command block or control
block is being addressed. These pins are multiplexed with
SA[2:0].
DISK CHIP SELECTS: DCS1# controls the ATA
command register block and corresponds to CS1FX# on
the IDE connector. DCS3# controls the ATA control
register block and corresponds to CS3FX# on the IDE
connector. These pins are multiplexed with SA[7,6].
DISK OUTPUT ENABLE: This signal controls the OE# of
the IDE isolation buffers. SMOUT5 is configured to enable
this function via the SMOUT Control Register.
PRELIMINARY
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