I82371MX Datasheet, PDF (75/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.3.2. ICW2—Initialization Command Word 2 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—021h
INT CNTRL-2—0A1h
All bits undefined
Write Only
ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address.
Bit
Description
7:3 Interrupt Vector Base Address: Bits [7:3] define the base address in the interrupt vector table
for the interrupt routines associated with each interrupt request level input.
2:0 Interrupt Request Level: Must be programmed to all 0s.
3.3.3.3. ICW3—Initialization Command Word 3 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—021h
All bits undefined
Write Only
The meaning of ICW3 differs between CNTRL-1 and CNTRL-2. On CNTRL-1, the master controller, ICW3
indicates which CNTRL-1 IRQ line physically connects the INTR output of CNTRL-2 to CNTRL-1.
Bit
Description
7:3
Reserved: Must be programmed to all 0s.
2
Cascaded Mode Enable: This bit must be programmed to 1 selecting cascade mode.
1:0
Reserved: Must be programmed to all 0s.
3.3.3.4. ICW3—Initialization Command Word 3 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-2—0A1h
All bits undefined
Write Only
On CNTRL-2 (the slave controller), ICW3 is the slave identification code broadcast by CNTRL-1.
Bit
Description
7:3
Reserved: Must be programmed to all 0s.
2:0
Slave Identification Code: Must be programmed to 010b.
PRELIMINARY
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