I82371MX Datasheet, PDF (49/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.42. LSBTDEV2—Local Standby Device 2 Timer Register
Address Offset:
Default Value:
Attribute:
B9h
00h
Read/Write
This register provides the idle time interval for generating an SMI#. An eight second internal clock provides an
idle timeout range of 8 sec. to 34 minutes. The timer is individually enabled via the LSBSMIE Register. The timer
can be frozen via the SYSMGNTC Register. The timer is reloaded with the count value programmed into this
register when there is an access to the enabled device address, the individual enable bit is set in the LSBSMIE
Register, or access to a device enabled in the LSBTRE register.
Bit
Description
7:0
LSTBY_TMR_DEV2. This field contains an 8-bit count value for the Device 2 Local Standby
Timer. (Programmable Address Range 1). 00h is an illegal programmed value.
3.2.43. LSBTDEV3—Local Standby Device 3 Timer Register
Address Offset:
Default Value:
Attribute:
BAh
00h
Read/Write
This register provides the idle time interval for generating an SMI#. An eight second internal clock provides an
idle timeout range of 8 sec. to 34 minutes. The timer is individually enabled via the LSBSMIE Register. The timer
can be frozen via the SYSMGNTC Register. The timer is reloaded with the count value programmed into this
register when there is an access to the enabled device address, the individual enable bit is set in the LSBSMIE
Register, or access to a device enabled in the LSBTRE register.
Bit
Description
7:0
LSTBY_TMR_DEV3. This field contains an 8-bit count value for the Device 3 Local Standby
Timer. (LTADEV3 Register). 00h is an illegal programmed value.
3.2.44. SESMIT—Software/EXTSMI# SMI Delay Timer Register
Address Offset:
Default Value:
Attribute:
BCh
00h
Read/Write
This timer is enabled via the GSMIE Register. When enabled, the timer provides a delay between a software
generated SMI# (setting the SWEXT_SMI_EN_SW bit in the GSMIE Register) or the generation of an EXTSMI#
(if enabled via the SYSSMIE Register), and the generation of the SMI# to the CPU. A 1 msec internal clock
provides a time delay range of 1 msec to 255 msec. The timer is reloaded when an enabled system event
occurs (see SYSEVNTE[2:0] Registers). When this timer generates an SMI, the global status bit for this timer
(GSMIS Register) and the individual status bit(s) for the source that caused the SMI are set.
Bit
Description
7:0
SWEXT_SMI_DLY_TMR. This field contains an 8-bit count value for the Software SMI and
EXTSMI# SMI Delay Timer. 00h is an illegal programming count.
PRELIMINARY
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