I82371MX Datasheet, PDF (44/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.31. LTADEV3—Local Trap Address for Device 3 Register
Address Offset:
Default Value:
Attribute:
A8h–A9h
00h
Read/Write
This register contains a 16-bit trap I/O address for device 3. The address range for this trap address is selected
via the LTMDEV3 Register.
Bit
Description
15:0
LTRP_ADDR_DEV3. Bits [15:0] correspond to PCI I/O address bits AD[15:0]. Note that
AD[31:16] must all be 0s for a match.
3.2.32. LTMDEV3—Local Trap Mask for Device 3 Register
Address Offset:
Default Value:
Attribute:
AAh
00h
Read/Write
This register selects the COM port access that will be trapped. The register also selects a trap address range of
1, 2, 4, or 8 bytes for Device 3 (split range is precluded).
Bit
Description
7:4
LTRP_COM_SEL. These bits select the COM port accesses that will be trapped. When a bit is
written to a 1, an access to the corresponding Local Trap Address will cause a synchronous
SMI#.
Bits COM Port Address
7
COM4 02E8h−02EFh
6
COM3 03E8h−03EFh
5
COM2 02F8h−02FFh
4
COM1 03F8h−03FFh
3:0
LTRP_MASK_DEV3. This field selects the I/O address trap range for Device 3.
1=corresponding address bit is not used in the address decode. 0=Corresponding address bit is
used in the address decode. For example, mask field=0011 selects a 4-byte range.
3.2.33. LTSMIE—Local Trap SMI Enable Register
Address Offset:
Default Value:
Attribute:
ABh
00h
Read/Write
This register enables the local address trap to cause a synchronous SMI for accesses to the corresponding
enabled trap address range. The address range for each bit is defined in Section 4.8.3.2, Access Ranges.
Bit
Description
7:6
Reserved.
5
LTRP_SMI_EN_IDE. 1=Enable. 0=Disable.
44
PRELIMINARY