I82371MX Datasheet, PDF (82/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Bit
Description
1
System Reset (SRST): This bit is used in conjunction with bit 2 in this register to initiate a hard
reset. When SRST =1, the MPIIX initiates a hard reset to the CPU when bit 2 in this register
transitions from 0 to 1. When SRST=0, the MPIIX initiates a soft reset when bit 2 in this register
transitions from 0 to 1.
0
Reserved.
3.3.5.5. Port 92 Register
Register Location:
Default Value:
Attribute:
92h
00h
Read/Write
This register controls the ALTA20 signal and initiates a fast soft reset by generating an INIT to the CPU.
Bit
Description
7:4 Reserved. Returns 0s when read.
3
Power On Password Protection: Writing a 1 to this bit enables the power-on password
protection by inhibiting accesses to the RTC CMOS RAM locations 38−3Fh. This is accomplished
by not issuing an RTCCS# for accesses to the data port (71h, 73h, 75h, 77h) after 38−3Fh has
been written to the index port (70h, 72h, 74h, 76h). This bit can only be cleared to 0 by turning off
system power (PCIRST# asserted) and then turning on system power.
2
Reserved. Returns 0 when read.
1
FASTA20. 0=ALTA20 signal is driven low. 1=ALTA20 signalis driven high. This signal is
externally OR’d with the Keyboard Controller A20 signal. This signal is connected to CPU for
support of real mode compatible software.
0
FASTINIT. This bit provides a fast software system reset function and is an alternate means to
reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real
Address Mode. FASTINIT provides a faster way of invoking a reset than is provided by the
Keyboard controller. Setting this bit to a 1 causes the INIT signal to pulse active (high) for
approximately 16 PCI Clocks. Before another INIT pulse can be generated, this bit must be set to
0.
82
PRELIMINARY