I82371MX Datasheet, PDF (119/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
Count: All timers use an 8 second internal clock period and can be programmed with an 8-bit value (up to 255,
00h is not legal) for an idle time-out range of 8 seconds to 34 minutes. This timer is reloaded with the initial count
value when there is an access to the device address or when the LSTBY_SMI_EN_xxx enable bit is set for that
device.
Freeze: The local idle timers will be frozen (i.e. enabled timers will stop the count down, while maintaining the
same values) when the SM_FREEZE bit is set. The SM_FREEZE bit is used by power management software
when a long service routine is started. The same software routine clears the SM_FREEZE bit before returning to
normal operation.
SMI Status: Local Idle SMI status is recorded in the GSMIS Register in the LSTBY_STAT bit when any local
standby timer generates an SMI#. Individual SMI status is recorded in the LSTBY_STAT_xxx bit for that
particular device.
4.8.3.4. Access Traps
Before power management software leaves the SMI# handler that places a device into a standby state, it must
enable the access trap for that device. Any access to an enabled trap range causes a synchronous SMI# to be
generated, so that power management software can return the device to an On state. Before leaving the power-
up routine, power management should enable the idle timer hardware to begin the cycle again.
Synchronous SMI#: The I/O trap SMI# is synchronous to the completion of the I/O instruction in the CPU. The
I/O instruction is completed when the Ready (RDY#, BRDY#) is returned to the CPU. MPIIX coordinates the
assertion of SMI# to the CPU with the generation of Ready to the CPU by the Mobile System Controller (MTSC)
such that the SMI# is generated at least 3 HCLKs before Ready is generated.
Enable: The Local Traps are globally enabled by setting the LTRP_SMI_EN bit in the GSMIE Register. When
this bit is set to 1, the enabling of the individual traps is controlled by the LTRP_SMI_EN_xxx for that specific
device.
SMI Status: Local Trap SMI status is recorded in the GSMIS Register in the LTRP_STAT bit when any local
trap generates an SMI#. Individual SMI status is recorded in the LTRP_STAT_xxx bit for that particular device.
4.8.3.5. SMOUT Programmable Outputs
Six output signals (SMOUT[5:0]) can be individually programmed to a 0 or 1 via the SMOUTC Register. These
signals provide the SL flexibility to control system power planes and isolation buffer output enables. It is
assumed that the above devices will be power managed in a centralized manner, while other devices will be
managed by the Keyboard (example: video), or self controlled (example: Super I/O chips).
4.8.4. SUSPEND
The Intel 430MX PCIset provides hardware to support two types of suspendSuspend-to-DRAM and Suspend-
to-Disk. The different suspend modes differ in the power saving and resume sequence latencies. The following
features are common to both suspend modes:
• Suspend is initiated by power management software in response to one of the special suspend SMI# events,
Suspend Resume Button (SRBTN#) and Battery Low (BATLOW#), or any other SMI#, depending on the
power management strategy.
• SMI# delay timers allow system activity to complete before starting the Suspend sequence.
• During the Suspend mode, only the 32 KHz RTC clock is active. All other clocks are stopped.
• MPIIX provides low power Resume logic that is clocked by the 32 KHz RTC clock. This allows the system to
use minimum power while monitoring Resume Events (COMRI#, IRQ8#, SRBTN#, and EXTSMI#). The
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