I82371MX Datasheet, PDF(104/133 Page) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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I82371MX Datasheet, PDF (104/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)

4.8. Power Management Support

The Intel 430MX PCIset power management provides flexible mechanisms to help the operating system and

system software manage the use of system resources for the lowest possible power consumption while

providing the best performance to the user.

MPIIX uses several mechanisms to help the power management software initiate and manage the transitions

between the power managed states. These include System-wide and Local Peripheral Event Monitors to identify

idle and wake-up conditions, Intelâs System Management Interrupt (SMI#) support, Advanced Power

Management (APM) interface, and PentiumÂ® Processor STPCLK# Clock Control, and Suspend/Resume

Hardware. MPIIX provides the following 3 basic areas of power management:

â¢ CPU Standby. When the operating system, application program, or system software is not doing useful

work, the CPU complex (CPU, DRAM, L2 Cache) does not need to be executing cycles and can therfore be

placed in a CPU Standby mode.

â¢ Local Standby. When a local peripheral, such as IDE hard disk or COM port, has not been used for a

specified amount of time, that peripheral can be placed in a Local Standby mode.

â¢ System Suspend. When the entire system has been idle for a specified amount of time or a critical system

event occurs, such as a battery low condition, the system will be put in itâs lowest power state.

Power Management Feature Summary

â¢ Power Management Initiation (SMI Generation)

ï£§ Global Standby Timer to Identify the System Idle Condition

ï£§ Software SMI#, External H/W SMI# (EXTSMI#)

ï£§ APM Software Initiated SMI#

ï£§ SMI# Generation Delay Timers

ï£§ SMI# Generation Status

ï£§ APM CallBack Feature

â¢ Power Management for CPU Complex: CPU, DRAM, L2 Cache ( CPU Standby)

ï£§ Flexible STPCLK# Mechanism for CPU Clock Control

â¢ With CPU CLK input running

â¢ With CPU CLK input Stopped

ï£§ Hardware Event Control for Wake-Up from STPCLK# (Stop Break Events)

ï£§ STPCLK# Duty Cycle Control for Low Frequency Emulation

ï£§ PCI Clock Control (CLKRUN#)

ï£§ APM Initiated Stop Clock Control

â¢ Power Management of Local Peripherals (Local Standby)

ï£§ Timers to Identify the Peripheral Idle Conditions

ï£§ Traps for Access to Powered-Down Peripherals

ï£§ SMOUT[5:0] Programmable Outputs for Power Plane Control

ï£§ Leakage Control for Powered-Down Peripherals

ï£§ SMI# Sequencing to CPU for I/O Cycle Restart

â¢ Power Management for System Suspend

ï£§ Suspend/Resume Button Input (SRBTN#)

ï£§ BATLOW# Indication Pin

ï£§ Shadow Registers for Standard AT Write-Only Registers

ï£§ DRAM Self-Refresh During Suspend

ï£§ âResume Wellâ To Monitor Wake-up Events During 0V Suspend

ï£§ Power-Down Leakage Control

ï£§ Resume Power and Reset Sequencing

104

PRELIMINARY

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