I82371MX Datasheet, PDF (48/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.39. LSBTAUD—Local Standby Audio Timer Register
Address Offset:
Default Value:
Attribute:
B5h
00h
Read/Write
This register provides the idle time interval for generating an SMI#. An eight second internal clock provides an
idle timeout range of 8 sec. to 34 minutes. The timer is individually enabled via the LSBSMIE Register. The timer
can be frozen via the SYSMGNTC Register. The timer is reloaded with the count value programmed into this
register when there is an access to the enabled device address, the individual enable bit is set in the LSBSMIE
Register, or access to a device enabled in the LSBTRE register.
Bit
Description
7:0
LSTBY_TMR_AUD. This field contains an 8-bit count value for the AUDIO Local Standby
Timer. 00h is an illegal programmed value.
3.2.40. LSBTCOM—Local Standby COM Timer Register
Address Offset:
Default Value:
Attribute:
B6h
00h
Read/Write
This register provides the idle time interval for generating an SMI#. An eight second internal clock provides an
idle timeout range of 8 sec. to 34 minutes. The timer is individually enabled via the LSBSMIE Register. The timer
can be frozen via the SYSMGNTC Register. The timer is reloaded with the count value programmed into this
register when there is an access to the enabled device address, the individual enable bit is set in the LSBSMIE
Register, or access to a device enabled in the LSBTRE register.
Bit
Description
7:0
LSTBY_TMR_COM. This field contains an 8-bit count value for the COM port Local Standby
Timer. 00h is an illegal programmed value.
3.2.41. LSBTDEV1—Local Standby Device 1 Timer Register
Address Offset:
Default Value:
Attribute:
B8h
00h
Read/Write
This register provides the idle time interval for generating an SMI#. An eight second internal clock provides an
idle timeout range of 8 sec. to 34 minutes. The timer is individually enabled via the LSBSMIE Register. The timer
can be frozen via the SYSMGNTC Register. The timer is reloaded with the count value programmed into this
register when there is an access to the enabled device address, the individual enable bit is set in the LSBSMIE
Register, or access to a device enabled in the LSBTRE register.
Bit
Description
7:0
LSTBY_TMR_DEV1. This field contains an 8-bit count value for the DEVICE 1 (PCS#) Local
Standby Timer. (Programmable Chip Select, PCS#). 00h is an illegal programmed value.
48
PRELIMINARY