I82371MX Datasheet, PDF (68/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.3.1.6. DS—DMA Status Register
Register Location:
Default Value:
Attribute:
Channels 0−3—08h
Channels 4−7—0D0h
00h
Read Only
Each DMA controller has a read-only DMA Status Register that indicates which channels have reached terminal
count and which channels have a pending DMA request.
Bit
Description
7:4
Channel Request Status. When a valid DMA request is pending for a channel (on its DREQ
signal line), the corresponding bit is set to 1. When a DMA request is not pending for a particular
channel, the corresponding bit is set to 0. Note that channel 4 is used to cascade the two DMA
controllers together and is not used for DMA transfers, so the response for a read of DMA2 status
for channel 4 is irrelevant.
Bit
Channel
4
0
5
1 (5)
6
2 (6)
7
3 (7)
3:0
Channel Terminal Count Status. 1=TC is reached; 0=TC is not reached.
Bit
Channel
0
0
1
1 (5)
2
2 (6)
3
3 (7)
3.3.1.7. DMA Base and Current Address Registers (8237 Compatible Segment)
Register Location:
Attribute:
DMA Channel 0—000h DMA Channel 4—0C0h
DMA Channel 1—002h DMA Channel 5—0C4h
DMA Channel 2—004h DMA Channel 6—0C8h
DMA Channel 3—006h DMA Channel 7—0CCh
Default Value: Undefined
Read/Write
This Register works in conjunction with the Low Page Register. After an autoinitialization, this register retains the
original programmed value. Autoinitialize takes place after a TC. The address register is automatically
incremented or decremented after each transfer. This register is read/written in successive 8-bit bytes. The
programmer must issue the "Clear Byte Pointer Flip-Flop" command to reset the internal byte pointer and
correctly align the write prior to programming the Current Address Register. Autoinitialize takes place only after a
TC.
Bit
Description
15:0
Base and Current Address [15:0]. These bits represent the 16 least significant address bits
used during DMA transfers. Together with the DMA Low Page Register, they form the ISA-
compatible 24-bit DMA address. Upon PCIRST or Master Clear, the value of these bits is
undefined.
68
PRELIMINARY