I82371MX Datasheet, PDF (71/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.2. TIMER/COUNTER REGISTERS
3.3.2.1. TCW—Timer Control Word Register
Register Location:
Default Value:
Attribute:
043h
All bits undefined
Write Only
The Timer Control Word Register specifies the counter selection, the operating mode, the counter byte
programming order and size of the count value, and whether the counter counts down in a 16-bit or binary-coded
decimal (BCD) format. After writing the control word, a new count can be written at any time. The new value
takes effect according to the programmed mode.
Bit
Description
7:6
Counter Select.
Bit [7:6] Function
00
Counter 0 select
01
Counter 1 select
10
Counter 2 select
11
Read Back Command
5:4
Read/Write Select.
Bit [5:4] Function
00
Counter Latch Command
01
R/W Least Significant Byte (LSB)
10
R/W Most Significant Byte (MSB)
11
R/W LSB then MSB
3:1
Counter Mode Selection. Bits [3:1] select one of six possible counter modes.
Bit [3:1] Mode Function
000
0
001
1
X10
2
X11
3
100
4
101
5
Out signal on end of count (=0)
Hardware retriggerable one-shot
Rate generator (divide by n counter)
Square wave output
Software triggered strobe
Hardware triggered strobe
0
Binary/BCD Countdown Select. 0=Binary countdown. The largest possible binary count is
2¹⁶. 1=Binary coded decimal (BCD) count is used. The largest BCD count allowed is 10⁴.
Read Back Command
The Read Back Command is used to determine the count value, programmed mode, and current states of the
OUT pin and Null count flag of the selected counter or counters. The Read Back Command is written to the
Timer Control Word Register which latches the current states of the above mentioned variables. The value of the
counter and its status may then be read by I/O access to the counter address. Note that The Timer Counter
Register bit definitions are different during the Read Back Command than for a normal Timer Counter Register
write.
PRELIMINARY
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