I82371MX Datasheet, PDF (26/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Address
0041h
0042h
0043h
0060h1
0061h
0070h1
0080h2
0081h
0082h
0083h
0084h2
0085h2
0086h2
0087h
0088h2
0089h
008Ah
008Bh
008Ch2
008Dh2
008Eh2
008Fh
0092h
00A0h
00A1h
00B2h
00B3h
00C0h
00C2h
00C4h
00C6h
00C8h
00CAh
00CCh
00CEh
00D0h
00D2h
00D4h
00D6h
00D8h
00DAh
FEDC
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Address
BA98
7654
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
010x
010x
010x
0110
0110
0111
100x
100x
1000
100x
100x
100x
100x
100x
100x
100x
100x
100x
100x
100x
100x
100x
1001
101x
101x
1011
1011
1100
1100
1100
1100
1100
1100
1100
1100
1101
1101
1101
1101
1101
1101
3210
0001
0010
0011
000
0001
0xx0
0000
0001
0010
0011
0100
0101
0110
0111
0100
1001
1010
1011
1100
1101
1110
1111
0010
xx00
xx01
0010
0011
000x
001x
010x
011x
100x
101x
110x
111x
000x
001x
010x
011x
100x
101x
Type
Name
R/W
Timer Counter 1 – Counter 1 Count
R/W
Timer Counter 1 – Counter 2 Count
wo
Timer Counter 1 Command Mode register
r
Reset XBus IRQ12/M and IRQ1
R/W
NMI Status and Control
wo
CMOS RAM Address and NMI Mask reg.
R/W
DMA Page Register (Reserved)
R/W
DMA Channel 2 Page register
R/W
DMA Channel 3 Page register
R/W
DMA Channel 1 Page register
R/W
DMA Page Register (Reserved)
R/W
DMA Page Register (Reserved)
R/W
DMA Page Register (Reserved)
R/W
DMA Channel 0 Page register
R/W
DMA Page Register (Reserved)
R/W
DMA Channel 6 Page register
R/W
DMA Channel 7 Page register
R/W
DMA Channel 5 Page register
R/W
DMA Page Register (Reserved)
R/W
DMA Page Register (Reserved)
R/W
DMA Page Register (Reserved)
R/W
DMA low page Register Refresh
R/W
System Control Port
R/W
INT 2 Control register
R/W
INT 2 Mask register
R/W
Advanced Power Management Control Port
R/W
Advanced Power Management Status Port
R/W
DMA2 CH0 Base and Current Address
R/W
DMA2 CH0 Base and Current Count
R/W
DMA2 CH1 Base and Current Address
R/W
DMA2 CH1 Base and Current Count
R/W
DMA2 CH2 Base and Current Address
R/W
DMA2 CH2 Base and Current Count
R/W
DMA2 CH3 Base and Current Address
R/W
DMA2 CH3 Base and Current Count
R/W
DMA2 Status(r) Command(w) register
wo
DMA2 Write Request register
wo
DMA2 Write Single Mask Bit
wo
DMA2 Write Mode register
wo
DMA2 Clear Byte Pointer
wo
DMA2 Master Clear
26
PRELIMINARY