I82371MX Datasheet, PDF (20/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Signal Name
EXTSMI#
EXTEVNT#/
MDRQ2
PAD# /
MDAK2#
Type
I
st
5/3V
pu8KΩ
CMOS
I
5V
pd50KΩ
TTL
O
5V
TTL
4mA
PCIRST#
High
Description
EXTERNAL SYSTEM MANAGEMENT INTERRUPT:
EXTSMI# is a falling edge triggered input to the MPIIX
indicating that an external device is requesting the
system to enter SMM mode. When enabled, a low level
on EXTSMI# will result in the assertion of the SMI#
signal. EXTSMI# is an asynchronous input and should
be asserted for a minimum of 32 µsec.
EXTERNAL EVENT (EXTEVNT#): The EXTEVNT#
signal allows events detected by the external logic to be
used as BSTCLK Events or CLKTHL Break Events.
MDRQ[2] is multiplexed with the EXTEVNT# signal. A
confguration bit selects which signal is enabled on the
pin. The power on default is the MDRQ[2] signal.
Peripheral Access Decode: The PAD# signal is
asserted by the MPIIX when a PCI memory or I/O
address is decoded to be in the same address range as
defined by the Peripheral Access Detect Tables and
enabled in the Peripheral Access Decode Enable
register. MPIIX does not have to be the target of the PCI
cycle for the PAD# signal to be asserted. MDAK2# is
multiplexed with the PAD# signal. A configuration bit
selects which signal is enabled on the pin. The power on
default is the MDAK2# signal.
2.8. System Clock And Reset Signals
Signal Name
Type
PCIRST#
Description
HCLK
I
5V
TTL
HOST CLOCK: Main system clock used to create
clocks for PCI, MTSC, MTDP, and external cache.
PCICLK
I
5V
TTL
PCI CLOCK: PCICLK provides timing for all
transactions on the PCI Bus. All other PCI signals are
sampled on the rising edge of PCICLK, and all timing
parameters are defined with respect to this edge. PCI
frequencies of 25–33 MHz are supported.
HCLKO
O
3.3V
TTL
4mA
Active
HOST CLOCK OUT: Must be buffered to provide CPU,
MTSC, TDP, and external L2 cache clocks.
PCICLKO
O
5V
TTL
4mA
Active
PCI CLOCK OUTPUT: Synchronous divide-by-2 of
HCLK. Must be buffered to provide fully loadable PCI
clock.
RTCCLK
I
5/3V
CMOS
REAL TIME CLOCK INPUT.
20
PRELIMINARY