I82371MX Datasheet, PDF (40/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.22. PMAM[1:0]—PROGRAMMABLE MEMORY ADDRESS MASK REGISTERS
Address Offset:
Default Value:
Attribute:
8Eh (PMAM0) and 8Fh (PMAM1)
00h
Read/Write
This register defines the size of the memory address range which will be decoded by MPIIX and used to signal
Burst Event, Clock Throttle Break Event or Peripheral Access Detect. The starting address is determined by
PMAC register programming.
Bit
Description
7:0
Memory Address Mask (MAM). This field provides mask bits that are used to determine if
AD[21:14] are part of the decode or ignored. Bits [7:0] correspond to AD[21:14], respectively. If
the bit is set to 1, the corresponding address bit is not used during the decode. Split ranges are
precluded.
3.2.23. PARE—PROGRAMMABLE ADDRESS RANGE ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
90h
00h
Read/Write
This register enables/disables the use of the address range defined in the Programmable Address Control
Registers (bits[5:1]) and the PCSC Register (bit 0). When enabled, the MPIIX forwards I/O accesses to the
address range specified by the corresponding PACx/PCSC Registers to the Extended I/O Bus. When disabled,
MPIIX does not claim these PCI I/O accesses. This register also enables PCS# assertion for accesses to
enabled PAC1 and PAC2 ranges.
Bit
Description
7
PCS# Enable for Programmable Address Range 2. 1=Enable (if bit 2=1). 0=Disable.
6
PCS# Enable for Programmable Address Range 1. 1=Enable (if bit 1=1). 0=Disable.
5
Programmable Address Range 5 Enable. 1=Enable. 0=Disable
4
Programmable Address Range 4 Enable. 1=Enable. 0=Disable
3
Programmable Address Range 3 Enable. 1=Enable. 0=Disable
2
Programmable Address Range 2 Enable. 1=Enable. 0=Disable
1
Programmable Address Range 1 Enable. 1=Enable. 0=Disable
0
PCS# Address Range Enable. 1=Enable. 0=Disable
40
PRELIMINARY