I82371MX Datasheet, PDF (112/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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4.8.2.2. Software Control of STPCLK#
The STPCLK# process is initiated by reading from the APMC Register. The MPIIX places the CPU into a Stop
Grant state (external CLK still applied to CPU) or places the CPU in a lower power Stop Clock state (external
CLK stopped to the CPU) depending on the STPCLK_MODE bit in the CLKC Register.
The system is brought out of the STPCLK# state when any enabled Stop Break Event occurs. Each of the Stop
Break Events can be individually enabled by writing a 1 to its enable bit in the Stop Break Enable Register and
all Stop Break Events can be disabled as a group by the STPBRK_EN bit to 0 in the STPBRKE2 Register. Stop
Break Events include IRQ[15:3,1], NMI, COMRI#, SMI#, INTR, SRBTN#, BATLOW#, and EXTSMI#. Stop break
events are not recognized until after the stop grant bus cycle has completed.
4.8.2.3. Emulating Clock Division (Clock Throttling)
When emulating clock division, the processor is running at full frequency for a pre-defined time period and then
is stopped for a pre-defined time period. The Run/Stop time interval ratio emulates the clock division effect from
a power/performance point of view. The clock division emulation is more effective than physically dividing the
processor frequency since upon a system Break Event the processor clock returns to full frequency. Also there
is no recovery time latency to start the clock. The clock division emulation is described in Figure 4.12. It works in
conjunction with the software driven Stop Clock feature.
Functional Description
Two programmable time intervals are provided to throttle the clock. The STPCLKHT Register defines the time
that the STPCLK# signal is negated, and the STPCLKLT Register defines the time that STPCLK# is asserted. A
single timer is loaded to count both intervals. To enable the CPU clock throttling the CLK_THROTTLE_EN bit
must be set to 1.
When enabled, the STPCLK# Timer is automatically loaded as follows:
• When STPCLK# is negated, the STPCLK# Timer is loaded from the STPCLKHT Register and the timer starts
counting down. When the timer reaches 00h, STPCLK# is asserted.
• When STPCLK# is asserted, the STPCLK# Timer is loaded from the STPCLKLT Register. When the timer
reaches 00h, STPCLK# is negated.
• While STPCLK# is negated, the STPCLK# Timer is loaded from the STPCLKHT Register when a Break Event
occurs. This prevents the CPU from entering a lower performance state if the system is active. Break Events
should be disabled if a constant lower frequency emulation is desired. Stop break events are not recognized
until after the stop grant bus cycle has completed.
The 8-bit STPCLK# Timer is clocked by a 32 usec clock. The STPCLKHT and STPCLKLT Registers allow
programming of the timing intervals for the assert/negate states of STPCLK#. The actual assertion and negation
time for STPCLK# is 2 counts greater that the programmed count. This allows a programmable interval from
approximately 96 µsec to 8 msec for both STPCLK# asserted and STPCLK# negated periods. The actual time
depends on the frequency of RTCCLK.
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PRELIMINARY