I82371MX Datasheet, PDF (5/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
3.2.67. STPBRKE2—Stop Break Event Enable 2 Register ....................................................................60
3.2.68. SHDW—Shadow Register Access Port ...................................................................................... 61
3.2.69. BSTCLKEE[6:0]—Burst Clock Event Enable Registers ............................................................. 63
3.2.70. CLKTHLBRKEE[6:0]—Clock Throttle Break Event Enable Registers ......................................64
3.3. ISA Compatible Registers ...................................................................................................................... 64
3.3.1. DMA REGISTERS........................................................................................................................... 64
3.3.1.1. DCOM—DMA Command Register .......................................................................................... 65
3.3.1.2. DCM—DMA Channel Mode Register ..................................................................................... 65
3.3.1.3. DR—DMA Request Register ...................................................................................................66
3.3.1.4. Mask Register—Write Single Mask Bit ................................................................................... 66
3.3.1.5. Mask Register—Write All Mask Bits ........................................................................................ 67
3.3.1.6. DS—DMA Status Register .......................................................................................................68
3.3.1.7. DMA Base and Current Address Registers (8237 Compatible Segment) ............................ 68
3.3.1.8. DMA Base and Current Byte/Word Count Registers (Compatible Segment) ....................... 69
3.3.1.9. DMA Memory Low Page Registers ......................................................................................... 69
3.3.1.10. DMA Clear Byte Pointer Register .......................................................................................... 70
3.3.1.11. DMC—DMA Master Clear Register ...................................................................................... 70
3.3.1.12. DCLM—DMA Clear Mask Register ....................................................................................... 70
3.3.2. TIMER/COUNTER REGISTERS ...................................................................................................71
3.3.2.1. TCW—Timer Control Word Register ....................................................................................... 71
3.3.2.2. Interval Timer Status Byte Format Register ............................................................................ 73
3.3.2.3. Counter Access Ports Register ............................................................................................... 73
3.3.3. INTERRUPT CONTROLLER REGISTERS .................................................................................. 74
3.3.3.1. ICW1—Initialization Command Word 1 Register ...................................................................74
3.3.3.2. ICW2—Initialization Command Word 2 Register ...................................................................75
3.3.3.3. ICW3—Initialization Command Word 3 Register ...................................................................75
3.3.3.4. ICW3—Initialization Command Word 3 Register ...................................................................75
3.3.3.5. ICW4—Initialization Command Word 4 Register ...................................................................76
3.3.3.6. OCW1—Operational Control Word 1 Register .......................................................................76
3.3.3.7. OCW2—Operational Control Word 2 Register .......................................................................77
3.3.3.8. OCW3—Operational Control Word 3 Register .......................................................................77
3.3.3.9. ELCR1—Edge/Level Triggered Register ................................................................................ 78
3.3.3.10. ELCR2—Edge/Level Triggered Register ............................................................................. 79
3.3.4. RESET EXTENDED I/O-BUS IRQ12 AND IRQ1 REGISTER ..................................................... 79
3.3.5. NMI REGISTERS ............................................................................................................................ 80
3.3.5.1. NMISC—NMI Status and Control Register ............................................................................. 80
3.3.5.2. NMI Enable and Real-Time Clock Address Register ............................................................. 81
3.3.5.3. Coprocessor Error Register .....................................................................................................81
3.3.5.4. RC—Reset Control Register ...................................................................................................81
3.3.5.5. Port 92 Register ........................................................................................................................ 82
3.4. Advanced Power Management Registers ............................................................................................ 83
3.4.1. APMC—ADVANCED POWER MANAGEMENT CONTROL PORT ........................................... 83
PRELIMINARY
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