I82371MX Datasheet, PDF (16/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Signal Name
RTCALE/
SMOUT4
SPKR
OSC
FERR#
IGNNE#
ALTA20M
Type
O
5V
TTL
4mA
O
5V
TTL
8mA
I
5V
TTL
I
3.3V
pu50KΩ
od
3.3V
O
5V
TTL
4mA
PCIRST#
High
Low
High
Low
Description
REAL TIME CLOCK ADDRESS LATCH: RTCALE is
used to latch the appropriate memory address into the
RTC. A write to port 70h, 72h, 74h, or 76h with the
appropriate RTC memory address that will be written to
or read from, causes RTCALE to be asserted. RTCALE
is asserted based on IOW# falling and remains asserted
for two SYSCLKs.
SPEAKER DRIVE: The SPKR signal is the output of
counter 2.
OSCILLATOR: OSC is the 14.31818 MHz ISA clock
signal. It is used by the internal 8254 Timer.
NUMERIC COPROCESSOR ERROR: This signal is tied
to the coprocessor error signal on the CPU. IGNNE# is
only used if the MPIIX coprocessor error reporting
function is enabled in the FDC Enable Register. If
FERR# is asserted, the MPIIX generates an internal
IRQ13 to its interrupt controller unit. The MPIIX then
asserts the INTR output to the CPU. FERR# is also used
to gate the IGNNE# signal to ensure that IGNNE# is not
asserted to the CPU unless FERR# is active. FERR#
has a weak internal pull-up used to ensure a high level
when the coprocessor error function is disabled.
IGNORE ERROR: This signal is connected to the ignore
error pin on the CPU. IGNNE# is only used if the MPIIX
coprocessor error reporting function is enabled in the
FDC Enable Register. If FERR# is asserted, indicating a
coprocessor error, a write to the Coprocessor Error
Register (F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error
Register is written, the IGNNE# signal is not asserted.
Alternative A20 MASK: This MPIIX output is externally
OR’d with the A20gate from the KBC to generate A20M#
to the CPU. A20M# is used to emulate the 1 Mbyte wrap-
around.
16
PRELIMINARY