I82371MX Datasheet, PDF (103/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
The MPIIX also supports a programmable interrupt (MIRQ). MIRQ is intended for use with motherboard devices
and can be routed to the any of the same 11 interrupts that the PIRQx# lines can be routed to using the MIRQ
Register. The routing accomplished in the same manner as for the PIRQx# inputs, except it is assumed that the
interrupts are active high. If interrupt steering is not required, the MIRQ register can be programmed to disable
routing.
IRQ[15:9,8#,7:1]
PIRQ[A:B]#
MIRQ
MPIIX
Interrupt
Steering
Logic
To
Internal
82C59s
052511
Figure 11. Interrupt Steering Logic
4.7.3. MOUSE FUNCTION
When the mouse interrupt function is enabled (via the FDC Enable Register), the mouse interrupt function is
provided on the IRQ12/M input signal. In this mode, a mouse interrupt generates an interrupt through IRQ12 to
the Host CPU. The MPIIX informs the CPU of this interrupt via a INTR. A read of 60h releases IRQ12. If the
IRQ12 function is enabled (mouse function disabled), a read of address 60h has no effect on IRQ12/M. Reads
and writes to this register flow through to the Extended I/O Bus. For additional information, see the IRQ12/M
description in the Signal Description.
4.7.4. COPROCESSOR ERROR FUNCTION
This function provides coprocessor error support for the CPU. This function is enabled via the FDC Enable
Register. FERR# is tied directly to the coprocessor error signal of the CPU. If FERR# is driven active to the
MPIIX, an internal IRQ13 is generated and an the INTR output from the MPIIX is generated. When a write to I/O
location F0h is detected, the MPIIX negates IRQ13 (internal to the MPIIX) and asserts IGNNE#. IGNNE#
remains asserted until FERR# is negated. Note, that IGNNE# is not driven active unless FERR# is active.
4.7.5. NMI SUPPORT
See Register Description.
PRELIMINARY
103