I82371MX Datasheet, PDF (22/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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3.0. REGISTER DESCRIPTION
There are two groups of MPIIX internal registersPCI Configuration Registers and ISA Compatible Registers.
These registers are discussed in this section.
Some of the MPIIX registers contain reserved bits. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for other bit positions and
then written back.
In addition to reserved bits within a register, the MPIIX contains address locations in the PCI configuration space
that are marked "Reserved" (Table 3.1). The MPIIX responds to accesses to these address locations by
completing the Host cycle. Software should not write to reserved MPIIX configuration locations in the device-
specific region (above address offset 3Fh).
During a hard reset the MPIIX sets its internal registers to predetermined default states. The default values are
indicated in the individual register descriptions.
The following notation is used to describe register access attributes:
RO
WO
R/W
R/WC
Read Only. If a register is read only, writes have no effect.
Write Only. If a register is write only, reads have no effect.
Read/Write. A register with this attribute can be read and written. Note that individual bits in some
read/write registers may be read only.
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
3.1. Register Access
Table 1 and Table 2 show the I/O assignments for the PCI Configuration Registers and ISA Compatible
Registers, respectively. CPU and PCI masters have access to all MPIIX internal registers.
The MPIIX is a single-function device on the PCI Bus. The MPIIX configuration registers are accessed through a
mechanism defined for single-function PCI devies in compliance with the PCI Local Bus Specification, Revision
2.0. The configuration registers can only be accessed by PCI masters. For configuration cycles, DEVSEL# is a
function of IDSEL and AD[1:0]. DEVSEL# is selected during a configuration cycle only if IDSEL is active and
both AD[1:0]=00. IDSEL must be connected to AD12 (device #1). Configuration cycles that target functions 1
through 7 (AD[10:8]=001b through 111b) are ignored (DEVSEL# is not asserted).
The ISA Compatible Registers (e.g., DMA registers, timer/counter registers, interrupt registers, X-Bus registers,
and NMI registers) are accessed through I/O space in the normal fashion. PCI master accesses to the ISA
Compatible Registers can be 8, 16, 24, or 32 bits. The MPIIX will only respond to the least significant byte (see
the IDE section in the Functional Description section for 16-bit IDE register response). On writes the other bytes
will not be loaded and on reads the other bytes have invalid data.
There are two power management registers located in normal I/O space. These registers are accessed (by PCI
Bus masters) with 8-bit accesses. The other power management registers are located in PCI configuration
space.
In general, accesses from CPU or PCI masters to the internal MPIIX registers are not broadcast to the Extended
I/O bus. Exceptions to this general rule are read and write accesses to locations 60h, 70–76h, and F0h, and
write accesses to ports 80h, 84−86h, 88h, 8C−8Eh. These accesses are broadcast to the Extended I/O Bus.
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PRELIMINARY