I82371MX Datasheet, PDF (87/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
4.2.3. PCI ARBITRATION
The MPIIX requests the use of the PCI Bus on behalf of Extended I/O DMA or PCI DMA. The MPIIX arbitrates
for the PCI Bus through the PHOLD# and PHLDA# signals. The PCI arbiter is assumed to be integrated in the
host-to-PCI bridge.
Extended I/O Bus DMA slave devices assert DREQ2 or MDRQ[2:0]# to gain access to the PCI Bus. The MPIIX
in response asserts PHOLD# to the PCI arbiter. For Extended I/O DMA devices, MPIIX keeps DACK2# or
MDAK[2:0]# negated until the MPIIX has ownership of the PCI Bus and Memory. The PCI arbiter asserts
PHLDA# to the MPIIX after its PCI buffers are emptied to PCI bus. The MPIIX gives ownership of the bus (PCI
and Memory) to the DMA controller after sampling PHLDA# asserted.
PCI DMA agents will use the PC/PCI REQ[A,B]# signals to gain access to the PCI bus. A PCI DMA agent can
be a PCI DMA slave, or a PCI expansion bridge that requests ownership of the PCI bus on behalf of an ISA
DMA slave or ISA master. The MPIIX obtains the PCI bus through the PHOLD#/PHLDA# sequence as
described for Extended I/O bus DMA. MPIIX then grants the bus to the PCI DMA agent by driving the
appropriate GNT[A,B]# signal as described later in the DMA chapter.
4.2.4. PCI CLOCK CONTROL (CLKRUN#)
MPIIX contains extensive power management capabilities. To provide power management on the PCI Bus,
MPIIX implements PCI clock control using the CLKRUN# signal. The three main states in the clocking protocol
are:
• Clock Running: The clock is running and the bus is operational.
• About to Stop: The central resource has indicated on the CLKRUN# line that the clock is about to stop.
• Clock Stopped: The clock is stopped with CLKRUN# being monitored for a restart.
MPIIX serves as the CLKRUN# Central Resource in accordance with the PCI Local Bus PCI Mobile Design
Guide, Revision 1.0.
4.3. Extended I/O Bus
The MPIIX incorporates a subset of the ISA Bus called the Extended I/O Bus that is designed to interface to 5V
peripherals that reside on the main system board. All PCI cycles intended for the Extended I/O bus are positively
decoded to allow a docking station bridge to claim subtractively decoded PCI cycles. The MPIIX does not
support bus masters on the Extended I/O Bus. The Extended I/O Bus provides the following support for
motherboard devices:
• IDE (16-bit) Interface with isolation buffer control.
• DMA between Extended I/O devices and PCI memory with steerable DMA channels (3).
• All ISA IRQ signals and 1 steerable Interrupt.
• BIOS ROM or Flash 256 Kbyte (8-bit) Interface.
• 6 Programmable I/O Decode Ranges.
• Audio (8-bit I/O and 8- or 16-bit DMA) Interface.
• Super-I/O (8-bit I/O and 8- or 16-bit DMA) Interface
• Keyboard Controller (8-bit) Interface.
• Real Time Clock (8-bit) Interface.
• Programmable chip select with isolation buffer control.
PRELIMINARY
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