I82371MX Datasheet, PDF (102/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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An I/O write to the CNTRL-1 or CNTRL-2 base address with data bit 4 equal to 1 is interpreted as ICW1. For
MPIIX-based ISA systems, three I/O writes to "base address + 1" (021h for CNTRL-1 and 0A0h for CNTRL-2)
must follow the ICW1. The first write to "base address + 1" (021h/0A0h) performs ICW2, the second write
performs ICW3, and the third write performs ICW4.
2. Operation Command Words (OCWs): These are the command words that dynamically reprogram the
interrupt controller to operate in various interrupt modes. Any interrupt lines can be masked by writing an OCW1.
A 1 written in any bit of this command word masks incoming interrupt requests on the corresponding IRQx line.
OCW2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode and to
control the End of Interrupt (EOI) function of the controller. OCW3 set up reads of the ISR and IRR,
enable/disables the Special Mask Mode (SMM), and sets up the interrupt controller in polled interrupt mode. The
OCWs can be written to the Interrupt Controller any time after initialization.
4.7.1.1. Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1. With MPIIX this bit is disabled and a new register
for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control
Registers ELCR1 and ELCR2. The default programming is equivalent to programming the LTIM bit (ICW1 bit 3)
to a 0 (all interrupts selected for edge triggered mode). Note, that IRQ0, 1, 2, 8#, and 13 can not be programmed
for level sensitive mode and can not be modified by software.
If an ELCR bit = 0, an interrupt request will be recognized by a low to high transition on the corresponding IRQx
input. The IRQ input can remain high without generating another interrupt. If an ELCR bit = 1, an interrupt
request will be recognized by a low level on the corresponding IRQ input and there is no need for an edge
detection. The interrupt request must be removed before the EOI command is issued to prevent a second
interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the
first INTA#. If the IRQ input goes inactive before this time, a default IRQ7 will occur when the CPU
acknowledges the interrupt. This can be a useful safeguard for detecting interrupts caused by spurious noise
glitches on the IRQ inputs. To implement this feature, the IRQ7 routine is used for "clean up" simply executing a
return instruction, thus ignoring the interrupt. If IRQ7 is needed for other purposes, a default IRQ7 can still be
detected by reading the ISR. A normal IRQ7 interrupt will set the corresponding ISR bit; a default IRQ7 will not
set this bit. If a default IRQ7 routine occurs during a normal IRQ7 routine, however, the ISR will remain set. In
this case, it is necessary to keep track of whether or not the IRQ7 routine was previously entered. If another
IRQ7 occurs, it is a default.
4.7.2. INTERRUPT STEERING
The MPIIX can be programmed to allow two PCI programmable interrupts (PIRQ[A,B]) to be internally routed to
one of 11 interrupts (IRQ15,14,12:9,7:3]. PCICLK is used to synchronize the PIRQx# inputs. The PIRQx# lines
are run through an internal multiplexer that assigns, or routes, an individual PIRQx# line to any one of 11 IRQ
inputs. The assignment is programmable through the PIRQx Route Control registers. One or more PIRQx# lines
can be routed to the same IRQx input. If interrupt steering is not required, the Route Registers can be
programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI Board to share a
single line across the connector. When a PIRQx# is routed to specified IRQ line, the software must change the
IRQ's corresponding ELCR bit to level sensitive mode. Note, that this means that the selected IRQ can no longer
be used by an another device, unless that device can respond as an active low level sensitive interrupt.
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PRELIMINARY