I82371MX Datasheet, PDF (9/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
1.0. ARCHITECTURE OVERVIEW
This section provides a brief overview of the MPIIX. More detailed descriptions are provided in the Signal
Description, Register Description, and Functional Description sections.
Power Management. Flexible power management capabilites of the MPIIX permit the operating system and
system software to efficiently manage the use of system resources. Various low power states are supported
while providing the best performance to the user. MPIIX uses several mechanisms to help the power
management software initiate and manage the transitions between the power managed states. These include,
System Event Monitors such as Idle Timers to identify peripheral and system-wide idle and wake-up conditions,
Intel’s System Management Interrupt (SMI) support, Advanced Power Management (APM) interface, Pentium®
Processor STPCLK# Clock Control, and Low Power Suspend/Resume hardware.
Docking Support. MPIIX provides the mechanisms necessary to implement a docking solution that supports
both PCI and ISA in the docking station. DMA information is sent across the PCI bus according to the PC/PCI
DMA expansion protocol. All ISA IRQx lines are provided. All cycles intended for the MPIIX are positively
decoded so that the bus bridge in a docking station can be the subtractive decode agent.
Fast IDE Interface. The MPIIX supports one IDE connector on the motherboard (up to 2 devices) and PIO IDE
transfers up to 14 Mbytes/sec. The IDE interface has a 2-word write poster and read prefetcher for optimal
transfers.
Plug-n-Play Interface. The MPIIX provides a Plug-n-Play interface for motherboard devices consisting of 3
steerable DMA channels, 1 steerable interrupt line, and 1 programmable chip select. Each steerable DMA
channel supports TYPE F transfers and can use a 4-byte buffer.
PCI Bus Interface. The MPIIX provides both a master and slave interface to the PCI bus. As a PCI master, the
MPIIX runs cycles on behalf of DMA. As a PCI slave, the MPIIX accepts cycles initiated by PCI masters
targeted for the MPIIX's internal register set or the Extended I/O bus. The MPIIX directly supports the PCI Bus
running at either 25 MHz or 30 MHz.
Extended I/O Bus. The MPIIX incorporates an 8-bit ISA-like interface for motherboard devices such as Multi-
Function I/O, Keyboard Controller, Audio Chip, ROM or Flash memory, and a Real Time Clock. MPIIX also
includes a 16-bit IDE interface. All cycles to this interface are positively decoded. One programmable Chip
Select I/O range, PCS#, and 5 additional programmable I/O ranges are provided for other devices on the
Extended I/O bus.
DMA. The DMA controller incorporates the functionality of two 82C37 DMA controllers with seven independently
programmable channels. Channels [3:0] are hardwired to 8-bit, count by bytes transfers, and channels [7:5] can
be programmed to either 16-bit, count by words transfers, or 8-bit transfers. All seven channels support fast
DMA type F timings using the steerable DMA channels.
Timer. The timer block contains three counters that are equivalent in function to those found in one 82C54
programmable interval timer. These counters provide the system timer function and speaker tone. The 14.31818
MHz oscillator input provides the clock source for the counters.
Interrupt Controller. The MPIIX provides an ISA compatible interrupt controller that incorporates the
functionality of two 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external
and 1 internal interrupts are possible.
PRELIMINARY
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